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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Leandro M. G. Rocha Morgana Macedo Guilherme Paim Eduardo Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) - Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program on Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9781728170442

ISBN: (纸本)9781728170459

Arithmetic operations are intrinsic to any embedded devices, and they usually have a significant impact on the circuit speed, area, and power consumption. Applications like video processing, digital signal processing, machine learning, among others, rely heavily on multipliers to execute their algorithms. Radix-2 m multipliers have been reported as one of the most power-efficient circuits. However, their architecture has not been explored nor optimized to improve the circuit quality. This work proposed two sign extension optimization techniques for these multipliers, aiming for better power efficiency and a smaller area. The baseline radix-4 (m=2) multiplier and its optimized versions were synthesized in a commercial 65nm technology to evaluate their performance. Results show that the optimized versions achieve power efficiency gains from 16.4% up to 78.6%, with circuit area reduction up to 49.2%.

关键词： Adders Optimization Power dissipation Computer architecture Digital signal processing Signal processing algorithms Standards

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Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture

Optimizing the Montgomery Modular Multiplier for a Power- an...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Mateus Terribele Leme Guilherme Paim Leandro M. G Rocha Patricia Ücker Vitor G. Lima Rafael Soares Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Graduate Program on Computer Science (PPGC) Federal University of Pelotas (UFPel)

ISBN: (数字)9781728180588

ISBN: (纸本)9781728180595

Cryptography hardware design is a key challenge towards the confidentiality advance in the prominent field of the internet of things (IoT). The rise of IoT embedded devices boosts the demand for power- and area- efficient solutions for cryptography hardware. The higher the robustness of the cryptography algorithm is, the higher are the hardware complexity, the circuit area, and energy consumption. Asymmetric algorithms are a particular class widely employed in ultra-secure cryptosystems. The high time-hardness to break the private-key in asymmetric algorithms is a result of its high mathematical complexity. RSA is an asymmetric algorithm that performs successive modular multiplications to encrypt and de-encrypt the information. Therefore, arithmetic operators are the most significant part regarding circuit area and power dissipation. This work evaluates a design space exploration for power- and area-efficient hardware VLSI design in the modular Montgomery multiplier employed in the RSA algorithm.

关键词： Hardware Computer architecture Adders Power dissipation Public key Very large scale integration

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CompressedMediQ: Hybrid Quantum Machine Learning Pipeline for High-Dimensional Neuroimaging Data

CompressedMediQ: Hybrid Quantum Machine Learning Pipeline fo...

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Acoustics, Speech, and Signal Processing Workshops (ICASSPW), IEEE International Conference on

作者： Kuan-Cheng Chen Yi-Tien Li Tai-Yu Li Chen-Yu Liu Po-Heng Henry Lee Cheng-Yu Chen Department of Electrical and Electronic Engineering Imperial College London London UK Centre for Quantum Engineering Science and Technology (QuEST) Imperial College London London UK Translational Imaging Research Center Taipei Medical University Hospital Taipei Taiwan Research Center for Neuroscience Taipei Medical University Taipei Taiwan Ph.D. Program in Medical Neuroscience College of Medical Science and Technology Taipei Medical University Taipei Taiwan National Center for High-Performance Computing NARlabs Hsinchu Taiwan Graduate Institute of Applied Physics National Taiwan University Taipei Taiwan Department of Medical Imaging Taipei Medical University Hospital Taipei Taiwan Department of Radiology National Defense Medical Center Taipei Taiwan Department of Radiology School of Medicine College of Medicine Taipei Taiwan

ISBN: (数字)9798331519315

ISBN: (纸本)9798331519322

This paper introduces CompressedMediQ, a novel hybrid quantum-classical machine learning pipeline specifically developed to address the computational challenges associated with high-dimensional multi-class neuroimaging data analysis. Standard neuroimaging datasets, such as large-scale MRI data from the Alzheimer’s Disease Neuroimaging Initiative and Neuroimaging in Frontotemporal Dementia, present significant hurdles due to their vast size and complexity. CompressedMediQ integrates classical HPC nodes for advanced MRI pre-processing and Convolutional Neural Network (CNN)-PCA-based feature extraction and reduction, addressing the limited-qubit availability for quantum data encoding in the NISQ era. This is followed by Quantum Support Vector Machine (QSVM) classification. By utilizing quantum kernel methods, the pipeline optimizes feature mapping and classification, enhancing data separability and outperforming traditional neuroimaging analysis techniques. Experimental results highlight the pipeline’s superior accuracy in dementia staging, validating the practical use of quantum machine learning in clinical diagnostics. Despite the limitations of NISQ devices, this proof-of-concept demonstrates the transformative potential of quantum-enhanced learning, paving the way for scalable and precise diagnostic tools in healthcare and signal processing.

关键词： Neuroimaging Support vector machines Quantum computing Accuracy Magnetic resonance imaging Pipelines Machine learning Medical services Signal processing Standards

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Consensus on Intervals of Communication Delay

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International Journal of Automation and computing 2018年第1期15卷 13-24页

作者： Heitor J.Savino Fernando O.Souza Luciano C.A.Pimenta Graduate Program in Electrical Engineering Federal University of Minas Gerais Institute of Computing Federal University of Alagoas Department of Electronic Engineering Federal University of Minas Gerais

This paper brings out a structured methodology for identifying intervals of communication time-delay where consensus in directed networks of multiple agents with high-order integrator dynamics is achieved. It is built upon the stability analysis of a transformed consensus problem which preserves all the nonzero eigenvalues of the Laplacian matrix of the associated communication topology graph. It is shown that networks of agents with first-order integrator dynamics can be brought to consensus independently of communication delay, on the other hand, for agents with second-order integrator dynamics, the consensus is achieved independently of communication delay only if certain conditions axe satisfied. Conversely, if such conditions axe not satisfied, it is shown how to compute the intervals of communication delay where multiple agents with second-order or higher-order can be brought to consensus. The paper is ended by showing an interesting example of a network of agents with second-order integrator dynamics which is consensable on the first time-delay interval, but as the time-delay increases, it loses consensability on the second time-delay interval, then it becomes consensable again on the third time-delay interval, and finally it does not achieve consensus any more on the fourth time-delay interval. This example shows the importance of analyzing consensus with time-delay in different intervals.

关键词： Time delay systems multi-agent systems consensus communication delay roots location.

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Approximate SATD Hardware Accelerator Using the 8 × 8 Hadamard Transform

Approximate SATD Hardware Accelerator Using the 8 × 8 Hadam...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Matheus F. Stigger Victor H. S. Lima Leonardo B. Soares Claudio M. Diniz Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Federal Institute of Rio Grande do Sul (IFRS) Rio Grande Brazil Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

Sum of Absolute Transformed Differences (SATD) is a distortion metric based on the Hadamard Transform. It is used in current video encoders inside the refinement stage of motion estimation, which decides the best block of pixels to be used as prediction for each block to be encoded. To reduce the computational effort incurred by the SATD calculation, this work proposes an approximate SATD hardware accelerator by excluding columns of adders/subtractors of the 8 × 8 Hadamard Transform (HT). The proposed approximate accelerator reduces energy by up to 40.78% compared to the precise SATD accelerator.

关键词： Transforms Computer architecture Hardware Video coding Adders Registers Software

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VLSI Design of Tree-Based Inference for Low-Power Learning Applications

VLSI Design of Tree-Based Inference for Low-Power Learning A...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Brunno A. Abreu Mateus Grellert Sergio Bampi Graduate Program in Microelectronics (PGMICRO) INF-UFRGS Federal University of Rio Grande do Sul Porto Alegre Brazil Department of Informatics and Statistics − INE Federal University of Santa Catarina (UFSC) Florianópolis Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

The use of Machine Learning techniques in battery-powered devices has increased in recent years. Therefore, evaluating power-accuracy trade-offs of inference models has become important. This work explores decision trees architectures, analyzing the effects of model complexity and approximation in power and accuracy. By quantizing the inputs to limited widths, we increased the accuracy of the models in up to 8.7% compared to precise cases. In terms of power, the variation in model complexity was more significant than in input width, as we obtained reductions of up to 97% by decreasing the tree depth, compared to 88% when decreasing the width.

关键词： Complexity theory Hardware Integrated circuit modeling Training Analytical models Decision trees Quantization (signal)

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Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators

Approximate Subtractor Operator for Low-Power Video Coding H...

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IEEE International Conference on electronics, Circuits and Systems

作者： Rafael Ferreira Mateus Leme Marcel Correa Luciano Agostini Claudio Diniz Bruno Zatt Graduate Program on Computer Science Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

Video coding requires a massive computational effort leading to large power dissipation and energy consumption. Thus, energy efficiency becomes a significant concern especially under limited energy resources such as in mobile devices. Approximate computing is a promising technique to improve energy efficiency. Therefore, this work presents a new approximate subtractor operator to be used in video coding hardware accelerators. The proposed subtractor reduces power of a Sum of Absolute Differences (SAD) hardware accelerator on approximately 10.39% (on average of different videos) when compared to the use of the subtractor from the synthesis tool. It also presents a power reduction of 18.13% when compared to state-of-the-art approximate adder.

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Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors

Maximizing the Power-Efficiency of the Approximate Pruned Mo...

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IEEE International New Circuits and Systems Conference

作者： Guilherme Paim Leandro M. G. Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil

This paper proposes the use of approximate adder compressors for a low-power 8-point Modified Rounded Discrete Cosine Transform (MRDCT_(10)) implementation. The algebraic approximation of the MRDCT was previously introduced in the literature, whose resultant matrix is only composed of 0, 1 and -1 values. Therefore, the MRDCT can be efficiently implemented using only adders and subtractors. We present an environment for the synthesis of the MRDCT in Cadence Encounter RTL Compiler tool. The synthesis reports are based on a set of real images as input vectors to obtain valid power results. Our results show that the use of approximate adder/subtractor compressors in hardwired state-of-the-art 8-point approximate MRDCT_(10) achieves savings ranging from 26% to 52.54% when compared with the macro function (+) from the tool.

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Exploring Architectural Solutions for an Energy-Efficient Kalman Filter Gain Realization

Exploring Architectural Solutions for an Energy-Efficient Ka...

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IEEE International Conference on electronics, Circuits and Systems (ICECS)

作者： Pedro T. L. Pereira Guilherme Paim Patrícia Ücker Eduardo Costa Sérgio Almeida Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil

The Kalman filter is a signal processing algorithm that plays an essential role in real-time mobile applications as nano drones navigation, spacecraft orbit control, GPS positioning, image recognition, and sensor data fusion for wearable health monitoring. However, the Kalman filter is a compute-intensive kernel since it implements a high amount of complex matrix operations like multiplications and inversions. The most timing-consuming tasks of the Kalman filter is the Kalman gain. Therefore, this work presents four architectural solutions to explore real-time and energy-efficient Kalman gain processing.

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Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation

Exploring Motion Vector Cost with Partial Distortion Elimina...

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IEEE International New Circuits and Systems Conference

作者： Brunno Abreu Mateus Grellert Guilherme Paim Thomas Fontanari Leandro M. G. Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program in Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

Integer Motion Estimation (IME) is one of the most costly steps in the video coding process, being responsible for 60% of the total encoding time. Two parameters are considered when calculating the redundancies (distortion) between video blocks: Sum of Absolute Differences (SAD) and motion vector cost (MV_(cost)). Partial Distortion Elimination (PDE) techniques may be used to optimize the calculation of the SAD unit itself, in order to avoid the computation of candidates that will certainly not be selected in the IME. This paper proposes an optimization in the distortion calculation by taking advantage of the PDE technique in SAD operation by including MVcost, in order to save even more cycles when compared to standard PDE usage, considering the High Efficiency Video Coding (HEVC) standard. We found out that the inclusion of MV_(cost) in the distortion cost achieves a quality increase of up to 1.28%. We compare three versions: adding MV_(cost) before/after SAD using a multiplexer, and before SAD with a Carry-Save Adder (CSA). The use of PDE including MV_(cost) before SAD calculation using a multiplexer achieves an average reduction of 17.5% in the energy consumption when compared to accumulating MV_(cost) after SAD. When using the CSA, we obtain an additional average reduction of 1.94%.

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