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Input optics systems of the KAGRA detector during O3GK (vol 2023, 023F01, 2023)

PROGRESS OF THEORETICAL AND EXPERIMENTAL PHYSICS 2023年第5期2023卷

作者： Akutsu, T. Ando, M. Arai, K. Arai, Y. Araki, S. Araya, A. Aritomi, N. Asada, H. Aso, Y. Bae, S. Bae, Y. Baiotti, L. Bajpai, R. Barton, M. A. Cannon, K. Cao, Z. Capocasa, E. Chan, M. Chen, C. Chen, K. Chen, Y. Chiang, C-I Chu, H. Chu, Y-K Eguchi, S. Enomoto, Y. Flaminio, R. Fujii, Y. Fujikawa, Y. Fukunaga, M. Fukushima, M. Furuhata, T. Gao, D. Ge, G-G Ha, S. Hagiwara, A. Haino, S. Han, W-B Hasegawa, K. Hattori, K. Hayakawa, H. Hayama, K. Himemoto, Y. Hiranuma, Y. Hirata, N. Hirose, E. Hong, Z. Hsieh, B-H Huang, G-Z Huang, H-Y Huang, P. Huang, Y-C Huang, Y-J Hui, D. C. Y. Ide, S. Ikenoue, B. Imam, S. Inayoshi, K. Inoue, Y. Ioka, K. Ito, K. Itoh, Y. Izumi, K. Jeon, C. Jin, H-B Jung, K. Jung, P. Kaihotsu, K. Kajita, T. Kakizaki, M. Kamiizumi, M. Kanbara, S. Kanda, N. Kang, G. Kataoka, Y. Kawaguchi, K. Kawai, N. Kawasaki, T. Kim, C. Kim, J. Kim, J. C. Kim, Ws Kim, Y-M Kimura, N. Kita, N. Kitazawa, H. Kojima, Y. Kokeyama, K. Komori, K. Kong, A. K. H. Kotake, K. Kozakai, C. Kozu, R. Kumar, R. Kume, J. Kuo, C. Kuo, H-S Kuromiya, Y. Kuroyanagi, S. Kusayanagi, K. Kwak, K. Lee, H. K. Lee, H. W. Lee, R. Leonardi, M. Li, K. L. Lin, L. C-C Lin, C-Y Lin, F-K Lin, F-L Lin, H. L. Liu, G. C. Luo, L-W Majorana, E. Marchio, M. Michimura, Y. Mio, N. Miyakawa, O. Miyamoto, A. Miyazaki, Y. Miyo, K. Miyoki, S. Mori, Y. Morisaki, S. Moriwaki, Y. Nagano, K. Nagano, S. Nakamura, K. Nakano, H. Nakano, M. Nakashima, R. Nakayama, Y. Narikawa, T. Naticchioni, L. Negishi, R. Quynh, L. Nguyen Ni, W-T Nishizawa, A. Nozaki, S. Obuchi, Y. Ogaki, W. Oh, J. J. Oh, S. H. Ohashi, M. Ohishi, N. Ohkawa, M. Ohta, H. Okutani, Y. Okutomi, K. Oohara, K. Ooi, C. Oshino, S. Otabe, S. Pan, K-C Pang, H. Parisi, A. Park, J. Arellano, F. E. Pena Pinto, I. Sago, N. Saito, S. Saito, Y. Sakai, K. Sakai, Y. Sakuno, Y. Sato, S. Sato, T. Sawada, T. Sekiguchi, T. Sekiguchi, Y. Shao, L. Shibagaki, S. Shimizu, R. Shimoda, T. Shimode, K. Shinkai, H. Shishido, T. Shoda, A. Somiya, K. Son, E. J. Sotani, H. Sugimoto, R. Suresh, J. Suzuki, T. Suzuki, T. Tagoshi, H. Takahashi, H Gravitational Wave Science Project National Astronomical Observatory of Japan 2-21-1 Osawa Mitaka City Tokyo 181-8588 Japan Advanced Technology Center National Astronomical Observatory of Japan 2-21-1 Osawa Mitaka City Tokyo 181-8588 Japan Department of Physics The University of Tokyo 7-3-1 Hongo Bunkyo-ku Tokyo 113-0033 Japan Research Center for the Early Universe The University of Tokyo 7-3-1 Hongo Bunkyo-ku Tokyo 113-0033 Japan Institute for Cosmic Ray Research KAGRA Observatory The University of Tokyo 5-1-5 Kashiwa-no-Ha Kashiwa City Chiba 277-8582 Japan Accelerator Laboratory High Energy Accelerator Research Organization (KEK) 1-1 Oho Tsukuba City Ibaraki 305-0801 Japan Earthquake Research Institute The University of Tokyo 1-1-1 Yayoi Bunkyo-ku Tokyo 113-0032 Japan Department of Mathematics and Physics Graduate School of Science and Technology Hirosaki University 3 Bunkyo-cho Hirosaki Aomori 036-8561 Japan Kamioka Branch National Astronomical Observatory of Japan 238 Higashi-Mozumi Kamioka-cho Hida City Gifu 506-1205 Japan The Graduate University for Advanced Studies (SOKENDAI) 2-21-1 Osawa Mitaka City Tokyo 181-8588 Japan Korea Institute of Science and Technology Information 245 Daehak-ro Yuseong-gu Daejeon 34141 Republic of Korea National Institute for Mathematical Sciences 70 Yuseong-daero 1689 Beon-gil Yuseong-gu Daejeon 34047 Republic of Korea International College Osaka University 1-1 Machikaneyama-cho Toyonaka City Osaka 560-0043 Japan School of High Energy Accelerator Science The Graduate University for Advanced Studies (SOKENDAI) 1-1 Oho Tsukuba City Ibaraki 305-0801 Japan Department of Astronomy Beijing Normal University Xinjiekouwai Street 19 Haidian District Beijing 100875 China Department of Applied Physics Fukuoka University 8-19-1 Nanakuma Jonan Fukuoka City Fukuoka 814-0180 Japan Department of Physics Tamkang University No. 151 Yingzhuan Road Danshui Dist. New Taipei City 25137 Taiwan Department of Physics

KAGRA, the underground and cryogenic gravitational-wave detector, was operated for its solo observation from February 25 to March 10, 2020, and its first joint observation with the GEO 600 detector from April 7 to April 21, 2020 (O3GK). This study presents an overview of the input optics systems of the KAGRA detector, which consist of various optical systems, such as a laser source, its intensity and frequency stabilization systems, modulators, a Faraday isolator, mode-matching telescopes, and a high-power beam dump. These optics were successfully delivered to the KAGRA interferometer and operated stably during the observations. The laser frequency noise was observed to limit the detector sensitivity above a few kilohertz, whereas the laser intensity did not significantly limit the detector sensitivity.

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Computation of resistance and potential of grounding grids in any geometry 16

Computation of resistance and potential of grounding grids i...

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16th International Conference on Environment and Electrical engineering, EEEIC 2016

作者： Pires, Thyago G. Nerys, Jose W. L. Silva, Carlos L. B. Oliveira, Diogo N. Filho, Antonio M. Silva Calixto, Wesley P. Alves, Aylton J. School of Electric and Computing Engineering Federal University of Goias Goiania Brazil Graduate Program in Electronic and Automation Systems Engineering University of Brasilia Brasilia Brazil Experimental and Technologic Research and Study Group Federal Institute of Education Science and Technology Goiania Brazil

ISBN: (纸本)9781509023196

This paper deals with the computation of ground resistance, surface voltage, touch voltage and step voltage, to mesh with horizontal wires arranged in different angles. The computer program implemented used in the mathematical modeling is based on the method proposed by Heppe, which allows obtaining the grounding parameters for homogeneous soil and soil stratified in two layers. The results obtained with the proposed method will be compared with other methods in literature. Also will be presented the results of a grounding grid using wires at various angles. © 2016 IEEE.

关键词： Mesh generation

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Optimization of grounding grid's multidesign geometry 16

Optimization of grounding grid's multidesign geometry

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16th International Conference on Environment and Electrical engineering, EEEIC 2016

作者： Silva, Carlos L. B. Oliveira, Diogo N. Pires, Thyago G. Nerys, Jose W. L. Barbosa, Paulo H. S. Calixto, Wesley P. Alves, Aylton J. Graduate Program in Electronic and Automation Systems Engineering University of Brasilia Brasilia Brazil School of Electric and Computing Engineering Federal University of Goias Goiania Brazil Experimental Technologic Research and Study Group Federal Institute of Education Science and Technology Goiania Brazil

ISBN: (纸本)9781509023196

This paper deals with the optimization of grounding grids geometry. The goal is to reduce the amount of material to deploy a grounding grid, while keeping the system security. The touch voltages, step voltages, GPR and ground resistance are parameters of grounding grids and are related to safety aspect. Also discussed is a genetic algorithm used for optimizing ground grids, which can assume any form in a limited space of the project. The simulation is based in images method. The results are presented and discussed. © 2016 IEEE.

关键词： Ground penetrating radar systems

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Using adder compressors for power-efficient 2-D approximate Discrete Tchebichef Transform

Using adder compressors for power-efficient 2-D approximate ...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Guilherme Paim Eduardo Costa Electronic Engineering Federal University of Pelotas (UFPel) Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

This paper proposes the use of efficient adder compressors for the power-efficient 2-D Discrete Tchebichef Transform (DTT) implementation. Due to the huge use of the discrete transforms in image compression, the search for efficient and fast approaches to the DCTs reached a special place in the state-of-art researches. The DTT represents a discrete class of the Chebyshev polynomials, and it is an alternative for the common DCT (Discrete Cosine Transform), which is present in several compression systems. High energy compaction and decorrelation are indicated as main properties of this transform. The approximate DTT performance combined with its lower computational effort makes this transform an excellent choice to be applied to dedicated hardware for image compression. As the resultant matrix of the state-of-the-art approximate DTT presents only 0, 1, -1, 2, and -2 values, thus it can be easily implemented in hardware using only adders and subtractors rather than general purpose multipliers. In this work we use combinations of efficient 4-2, 6-2, and 8-2 adder compressors for the state-of-the approximate DTT implementations. We present an environment for the synthesis of the DTT in Cadence Encounter RTL Compiler tool. The synthesis reports are based on a set of true images as input vectors in order to obtain valid power results. The results show that the hardwired state-of-the-art approximate DTT solutions, with adder compressors, minimizes both cells area and power dissipation, when compared with the native DCT.

关键词： Adders Compressors Discrete cosine transforms Image coding Computer architecture Hardware

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Exploiting adder compressors for power-efficient 2-D approximate DCT realization

Exploiting adder compressors for power-efficient 2-D approxi...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Tiago Schiavon Guilherme Paim Mateus Fonseca Eduardo Costa Sergio Almeida Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Electronic Engineering - Engineering Center (CEng) Federal University of Pelotas (UFPel) Graduate Program on Health and behavior Catholic University of Pelotas (UCPel)

This paper proposes the use of efficient adder compressors for the power-efficient 2-D Discrete Cosine Transform (DCT) implementation. Due to the increasing use of the discrete transforms in image compression, and its dedicated hardware design, the search for efficient and fast approaches to the DCTs reached a special place in the state-of-art researches. The DCT is an approximation of the cosine function, whose resultant matrix is only composed of 0 and 1 values. Therefore, the DCT can be easily implemented using only adders and subtractors rather than general purpose multipliers. In this work we use combinations of efficient 4-2 and 8-2 adder compressors for the state-of-the approximate DCT implementations. The approximate DCT performance combined with its lower computational effort makes this transform an excellent choice to be applied to dedicated hardware for image compression. We present an environment for the synthesis of the DCTs in Cadence Encounter RTL Compiler tool. The synthesis reports are based on a set of true images as input vectors in order to obtain valid power results. The results show that the hardwired state-of-the-art approximate DCT solutions, with adder compressors, minimizes both cells area and power consumption with good overall quality images.

关键词： Discrete cosine transforms Adders Compressors Image coding Hardware Computer architecture

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Power-efficient sum of absolute differences architecture using adder compressors

Power-efficient sum of absolute differences architecture usi...

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IEEE International Conference on electronics, Circuits and Systems (ICECS)

作者： Bianca Silveira Guilherme Paim Cláudio M. Diniz Eduardo A. C. da Costa Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Electronic Engineering - Engineering Center (CEng) Federal University of Pelotas (UFPel) Pelotas Brazil

ISBN: (纸本)9781509061143

The calculation of the Sum of Absolute Differences (SAD) is one of the most time-consuming operations of the video encoder compatible with the new High Efficiency Video Coding (HEVC) standard. SAD hardware architecture employs an adder tree to accumulate the coefficients from absolute difference between two video blocks. This paper proposes the exploration of the different adder compressors structures in the SAD hardware architecture. The architectures were synthesized to 45nm standard cells. Synthesis results show that SAD architecture with adder compressors with Kogge-Stone adders in the recombination line reduces power dissipation in 60.8% on average when compared with SAD architecture using conventional adders from the synthesis tool.

关键词： Adders Compressors Computer architecture Hardware Video sequences Power dissipation Standards

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Design of optimized radix-2 and radix-4 butterflies from FFT with decimation in time

Design of optimized radix-2 and radix-4 butterflies from FFT...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Renato Neuenfeld Mateus Fonseca Eduardo Costa Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Engineering Center Federal University of Pelotas (UFPel) Pelotas Brazil

In the FFT computation, the butterflies play a central role, since they allow calculation of complex terms. In this calculation, involving multiplications of input data with appropriate coefficients, the optimization of the butterfly can contribute for the reduction of power consumption of FFT architectures. In this paper different and dedicated structures for the 16 bit-width radix-2 and radix-4 DIT butterflies are implemented, where the main goal is to minimize the number of arithmetic operators in order to produce power-efficient structures. Firstly, we improve a radix-2 butterfly previously presented in literature, reducing one adder and one subtractor in the structure. After that, part of this optimized radix-2 butterfly is used to reduce the number of real multipliers in the radix-4 butterfly. The main results show that the optimization guarantees reduced power consumption for radix-2 butterfly, when compared with previous works from the literature. Moreover, the use of part of the optimized radix-2 into the radix-4 structure leads to the reduction of power consumption for this structure.

关键词： Computer architecture Adders Optimization Power demand Delays Microprocessors

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Exploiting architectural solutions for IIR filter architecture with truncation error feedback

Exploiting architectural solutions for IIR filter architectu...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Gustavo Ott Eduardo Costa Sergio Almeida Mateus Fonseca Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Engineering Center Federal University of Pelotas (UFPel) Pelotas Brazil

Digital filters are widely used in digital systems, which can make use of integer arithmetic to achieve higher performance. The use of integer operands can compromise the filter operation, due to the inherently error caused by truncation operations. Addressing this kind of problem, we propose an IIR filter for biomedical signals using the truncation error feedback (TEF), in which a feedback signal is obtained from the division remainder of the truncation operation. Two dedicated fully-sequential and parallel architectures were implemented and simulated using VHDL language, and synthesized in Cadence environment using the 45 nm Nangate Open Cell Library. A simulated ECG signal was used as input to verify the functionality of an IIR high pass filter with TEF. The results of our analysis indicate that the use of TEF can be an important approach in digital systems, where integer arithmetic for computation is adequate for performance requirements. Using this feedback signal, the design specifications of the filter remained significantly the same compared to the filter specification, independently of the cut-off and sample frequency ratio.

关键词： Finite wordlength effects Electrocardiography Cutoff frequency Computer architecture MATLAB Quantization (signal)

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A power-efficient imprecise radix-4 multiplier applied to high resolution audio processing

A power-efficient imprecise radix-4 multiplier applied to hi...

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IEEE International Conference on electronics, Circuits and Systems (ICECS)

作者： Guilherme Paim Leonardo Soares Julio F. R. Oliveira Eduardo Costa Sergio Bampi Electronic Engineering - Engineering Center (CEng) Federal University of Pelotas (UFPel) Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (纸本)9781509061143

This paper presents an power-efficient imprecise radix-4 multiplier applied to filtering Hi-Res (High Resolution) audio. The proposed multiplier was based on an imprecise 2×2 (m=2) multiplication block in order to implement optimized 2's complement radix-2 m array multipliers. The imprecise 2×2 multiplication block was previously proposed in literature, and presents as main characteristic a tunable error that enables the building of an imprecise radix-4 multiplier with a reduced number of logic gates. Since in the radix-2 m multiplier architecture the operands are split into groups of m bits, then, the m=2 imprecise multiplier is used as a basic component in its structure. Our work deals with different levels of approximation in the radix-2 m multiplier. We present four different approximate radix-4 multipliers architectures to be used in sequential FIR filters implemented in hardware. The filters are described in VHDL and synthesized for ASIC in Cadence RTL Compiler tool using Nangate 45nm standard cells. The power reports are evaluated using real input vectors from Hi-Res audio sequences in order to obtain valid power dissipation results. The imprecise FIR filters present area and power reductions of up to 5.7% and 12.5% when compared to the precise designs without compromising the Signal to Noise Ratio (SNR) of recorded 24-bit@192kHz Hi-Res audio signals.

关键词： Finite impulse response filters Signal to noise ratio Computer architecture Logic gates MATLAB Periodic structures Power dissipation

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A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding

A novel pruned-based algorithm for energy-efficient SATD ope...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Leonardo Bandeira Soares Cláudio Machado Diniz Eduardo Antonio César da Costa Sergio Bampi Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program on Electronic Engineering and Computing (PPGEEC) Catholic University of Pelotas (UCPEL) Pelotas Brazil

This paper proposes a novel approximate computing algorithm for the Sum of Absolute Transformed Differences (SATD) to meet energy efficiency in CMOS accelerator circuits. It is based on the pruning of least significant coefficients in the 2-D Hadamard Transform (HT) which is the most compute intensive kernel in the SATD. The SATD is a metric for block matching that is used in video coding standards like the new High Efficiency Video Coding (HEVC). This metric is used to provide better results in mode decision when compared to the Sum of Absolute Differences (SAD) at the expense of larger amount of arithmetic operations as well as higher energy consumption. We present 6 different approximate SATD 4×4 architectures that were synthesized for a 45 nm PDK. Results for the approximate architecture with 10 discarded HT coefficients show energy per operation reduction of 70.7% and BD-PSNR reduction of just -0.008 dB, for a 1080p video sequence.

关键词： Transforms Approximation algorithms Computer architecture Energy efficiency Video coding Computational efficiency Approximate computing

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