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IEEE Design and Test 2025年

作者： Ferreira, Állan F. G. Zilch, Lucas B. Lubaszewski, Marcelo S. Balen, Tiago R. Universidade Federal Do Rio Grande Do Sul Graduate Program in Microelectronics - PGMICRO Porto Alegre Brazil

This work introduces a machine learning method for indirect test pattern generation in analog and mixed-signal circuits. The proposed method employs a low-cost test generation tool to simulate circuit specifications and parametric measures, incorporating variability via Monte Carlo simulation. Learning models are trained to relate low-cost DC node measurements to circuit specifications, enabling indirect testing. Validation on a 180 nm fully-differential integrated filter achieved R2 scores of 0.76 for DC gain, 0.76 for cutoff frequency, and 0.98 for slew rate. A simulation fault injection campaign using a structural fault model (catastrophic and parametric faults) demonstrated 100% fault coverage with 19 measurements. © 2013 IEEE.

关键词： Mixed signal integrated circuits

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Cross-Section Estimation for Assessment of Circuit Susceptibility to Radiation

Cross-Section Estimation for Assessment of Circuit Susceptib...

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Latin American Test Workshop, LATW

作者： Clayton R. Farias Tiago R. Balen Paulo F. Butzen Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9798350365559

ISBN: (纸本)9798350365566

The aggressive scaling of nanometric VLSI technologies increases the integrated circuits susceptibility to radiation, especially to single-event effects. Ordinarily, circuit vulnerability is evaluated through the cross-section metric, which represents the number of errors observed in a given time window, divided by the particle fluence (integral of flux) passing through the circuit in the same time frame. Obtaining the cross-section requires performing an expensive radiation test. Therefore, any way of predicting it, even with a loss in accuracy, is important to allow early design choices to reduce the expected error rate of an electronic circuit intended to be deployed in radiation environments. In this context, this work proposes a methodology framework to evaluate cross-sections of combinational standard cells against radiation-induced errors. The procedure extracts the most sensitive cell areas according to input vectors, indicating the radiation-sensitive charge collection areas. This study suggests different approaches to evaluate the cross-section through physical design characteristics. First, it explores the scenario for low LET particles, identifying the charge collection areas. Subsequently, it considers the heavy ions particle range to estimate the maximum cross-section. Results indicate that cross-section is almost 9.5 times lower for low-energy particles. Literature results suggest that charge collection could arise outside the sensitive plane. This finding could lead to further investigation, and the method proposed can serve as an effective alternative for estimating circuit cross-section.

关键词： Measurement Layout Estimation Very large scale integration Logic gates Ions Vectors

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Exploring Parallelism in ZynqNet AI Engine to Accelerate Image Classification in Aerospace

Exploring Parallelism in ZynqNet AI Engine to Accelerate Ima...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Eduardo Marañon Aguilar Fabio Benevenuti Fernanda Lima Kastensmidt Federal University of Rio Grande do Sul (UFRGS) Institute of Informatics Microelectronics Graduate Program (PGMICRO) Porto Alegre Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

This research investigates various configurations of the Zynqnet AI Engine to accelerate image classification tasks using the SAT-6 dataset and a 4-layer CNN. The C++ code for the hardware accelerator was translated into RTL using Vivado HLS and integrated with the Zynq Processing System on a ZedBoard Zynq-7000 ARM/FPGA SoC. The AI engine was configured to work with 32 -bit floating point, 8bit fixed point and 8 -bit integer type operations, with different processing elements for parallelizing CNN tasks. Given a 64-bit data memory bus in communication with the accelerator and an 8-bit integer quantization, the variation in the number of processing elements does not result in a significant performance improvement. To address this, 8 values were grouped for reading and writing in 64-bit parallel mode, and different communication architectures were designed to improve data transfer between the accelerator and DDR memory, with optional enablement of L1D and L2 cache. The research analyzes CNN computation performance and FPGA resource usage (LUTs, FFs, BRAMs, DSPs) across configurations, providing insights into the trade-offs in FPGA-based CNN implementations, aiding the development of efficient, high-performance hardware accelerators for Deep Learning applications.

关键词： Quantization (signal) Writing Table lookup System-on-chip Convolutional neural networks Artificial intelligence Hardware acceleration Engines Field programmable gate arrays Image classification

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An Energy-Efficient Interpolation Unit Targeting VVC Encoders with Approximate Adder

An Energy-Efficient Interpolation Unit Targeting VVC Encoder...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Rafael Da Silva Mateus Grellert Ricardo Reis Graduate Program in Microelectronics - PGMICRO Federal University of Rio Grande do Sul - UFRGS Brazil

The advances in current video encoders allow significant compression at the cost of increased computing and energy consumption. This creates a demand for the development of dedicated accelerators that efficiently explore the parallelism of computing-intensive encoding operations. This work presents a hardware accelerator for the interpolation step of Versatile Video Coding (VVC) systems using Lower-Part-OR Adders (LOA). Unlike competing solutions, the proposed design fully complies with current VVC interpolation types, including the alternative filter of this standard. A data gating mechanism is also implemented to prevent unnecessary circuit switching. Experimental results show that savings of up to 78.51 % in power and 67.08% in gate count can be achieved by using approximate computing techniques.

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Hardening a RISC-V Softcore for Embedded Aerospace Applications in SRAM-based FPGA

Hardening a RISC-V Softcore for Embedded Aerospace Applicati...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Eduardo Marañon Aguilar Fabio Benevenuti Fernanda Lima Kastensmidt Institute of Informatics Microelectronics Graduate Program (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9798350391695

ISBN: (纸本)9798350391701

We investigate the implementation of triple modular redundancy (TMR) with different number of voters in a softcore RISC-V microprocessor to mitigate radiation-induced faults in the configuration memory (CRAM) of SRAM-based FPGA. The case-study microprocessor is the Steel Core implemented in AMD Xilinx 7-Series/Zynq-7000 device, executing benchmark software on the FreeRTOS operating system. We implemented coarse-grained TMR (CGTMR) and fine-grained distributed TMR (FGDTMR) using an automated redundancy and voter insertion tool. TMR is used in combination with memory scrubber featured by the FPGA hardware, which uses error correction codes (ECC) to revert radiation-induced faults in CRAM. Fault injection in CRAM emulating radiation-induced faults is used to evaluate the benefits of both TMR and ECC. Under fault injection, combining the fault masking capability of TMR with the self-healing by ECC, improved mean time between failures (MTBF) up to 5×. ECC alone did not improve significantly the fault tolerance. Without ECC, FGDTMR improves MTBF in 2×, but at a higher cost in circuit area and resources usage. When combined with ECC, the CGTMR provides fault tolerance comparable to FGDTMR but with 30% less resources usage.

关键词： Prevention and mitigation Microprocessors Redundancy Fault tolerant systems Software Error correction codes Software reliability Circuit faults Steel Field programmable gate arrays

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Quality-Reconfigurable Approximate Multiplier Utilizing Select Leading One-Bit Blocks

Quality-Reconfigurable Approximate Multiplier Utilizing Sele...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： João M. Bedin Pedro T. L. Pereira Rodrigo N. Wuerdig Eduardo Da Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) - Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program in Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

Multipliers are essential for emerging technologies, as they are vital arithmetic circuits in many energy-efficient applications, such as digital signal processing and machine learning applications. Approximate multipliers (AxM) became an optimal option for applications in ASIC systems with error tolerance. This paper proposes to develop a run-time reconfigurable AxM with four approximation levels in a single circuit, evaluating accuracy and circuit metrics (e.g., circuit area, timing, and power consumption) based on the leading one-bit-based approximate (LoBA) multiplier. The results achieve a circuit area reduction of 52% less area and up to 27% less power consumption when compared with equivalent architecture based on LoBA state-of-art. Applying the proposed RLoBA to a normalized least mean square (NLMS) adaptive filter case study, we obtain 22.95% less power consumption using dynamic approximate level selection than the precise multiplier while maintaining the same accuracy level.

关键词： Measurement Power demand Accuracy Circuits Adaptive filters Machine learning Lead Timing Reconfigurable architectures Standards

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Energy-Efficient Hardware Architecture for VVC TZS Using Approximate Subtractors

Energy-Efficient Hardware Architecture for VVC TZS Using App...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Rafael Ferreira Luciano Agostini Cláudio M. Diniz Bruno Zatt Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Pelotas RS Brazil Microelectronics Group (GME) Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

This paper investigates the impact of approximate subtractors in the hardware architecture of the Sum of Absolute Differences (SAD) computation within the Test Zone Search (TZS) algorithm, commonly used in current video encoders like the Versatile Video Coding (VVC). Four state-of-the-art imprecise subtractors $(AppS, AXSC1, AXSC2, AXSC3)$ were analyzed across various video resolutions to assess their influence on computational effort, energy consumption, and coding efficiency. The results show that subtractors like $AppS_{4}$ and $AXCS1_{4}$ provide significant reductions in energy consumption with minimal impact on video coding quality. These findings are especially relevant for low-power devices and embedded systems, where energy efficiency is critical. The use of imprecise subtractors offers a promising tradeoff between computational efficiency and energy savings, making them a viable solution for high-performance video encoders.

关键词： Video coding Energy consumption Embedded systems Energy conservation Energy resolution Computer architecture Energy efficiency Hardware Computational efficiency Power dissipation

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LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical Characterization

LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input ...

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IEEE Computer Society Annual Symposium on VLSI

作者： Rodrigo N. Wuerdig Vitor H. Maciel Ricardo Reis Sergio Bampi Graduate Program in Microelectronics (PGMICRO) Universidade Federal do Rio Grande do Sul (UFRGS) Porto Alegre Brazil

The characterization of logic cells is a critical step in the design of digital circuits. Existing open-source cell characterization tools typically require significant extra information beyond the SPICE netlist. In this paper, we present a new open-source tool - LEX - that serves as a very useful interface for these characterization tools, enabling the extraction of essential input and output information, Boolean expressions, truth tables, and transition (switching) arcs directly from the SPICE netlist. Our LEX tool offers several advantages over existing open-source methods. First, it simplifies the cell electrical characterization process by eliminating the need for manual input of additional information. This saves time and reduces the incidence of errors. Second, our tool provides a more comprehensive set of information than existing tools, including Boolean expressions and truth tables. Third, LEX is highly flexible and can be integrated with a wide range of existing open-source cell characterization tools. We conducted experiments using a test set of netlists to demonstrate LEX effectiveness. By providing a more comprehensive set of information, eliminating the need for manual input of additional information, and improving efficiency, our tool offers a powerful new option to be integrated into already existing and future open-source characterization tools.

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A Design Framework for Neural Network Architecture Exploration

A Design Framework for Neural Network Architecture Explorati...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Luis Antonio Spader Simon Lucas Soares Brunno Abreu Mateus Grellert Embedded Computing Laboratory (ECL) Federal University of Santa Catarina (UFSC) Brazil Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do SuI (UFRGS) Brazil

The use of neural networks (NNs) has significantly increased due to their ability to solve complex problems in different domains. NNs are increasingly being employed in embedded applications, so energy-efficient solutions are critical to enabling the wide adoption of such technologies. However, the flexibility of NNs makes the design of accelerators quite challenging, as there are many architectural parameters that must be optimized for each case, such as the number of inputs, input width, number of pipeline stages, activation functions, etc. This work proposes a framework that provides an automatic generation of RTL descriptions of NN architectures to expedite design space exploration. To show the usefulness of our solution, we compare several NN models in terms of important design parameters such as area and power, along with a model accuracy performance. Special attention should be given to carefully managing the bit width. Additionally, when prioritizing model accuracy, careful consideration of the bit width and the number of hidden layers is essential, as hidden layers may contribute to propagated errors.

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An Optimized VLSI Exponential Unit Design Exploring Efficient Arithmetic Operation Strategies

An Optimized VLSI Exponential Unit Design Exploring Efficien...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Patrícia Da Costa Morgana Da Rosa Rafael Soares Eduardo Da Costa Sergio Bampi Graduate Program on Microelectronics Federal University of Rio Grande do Sul Porto Alegre Brazil Graduate Program on Computing Federal University of Pelotas (UFPel) Pelotas Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

This work presents an optimized exponential function VLSI hardware design by Taylor series expansion. The proposed architecture implements the exponential by approximating the logic design of a 4 th -order Taylor series and explores efficient CMOS arithmetic operation strategies. It implements a shift-based divider and explores an efficient 4-2 adder compressor in the adder tree. The proposal with a −7 to 11 input values range shows an output error of around 2% of MRED with a reduced energy consumption of 3.63 pJ/operation for 32-bit output. For a 64-bit output, the energy per operation of the VLSI exponential unit is 14.97pJ/op, being able to process a more comprehensive input range (i.e., −14 to 22) for a negligible mean output error of around 1.7% of MRED.

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