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AxASRE: A Novel Approach to Approximate Adder Synthesis Results Estimation.

AxASRE: A Novel Approach to Approximate Adder Synthesis Resu...

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International Conference on Dependable Systems and Networks Workshops (DSN-W)

作者： Pedro T. L. Pereira Guilherme Paim Paulo Flores Eduardo Costa Sergio Bampi Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil INESC-ID Instituto Superior Técnico ULisboa Portugal Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil

Thanks to the high energy efficiency achieved by approximate circuits, the exploration of approximate solutions for a wide of applications is the focus of academic and industrial research. However, defining the most appropriate approximation considering the power consumption and accuracy trade-off can be exhaustive. This paper proposes a novel approach to estimate the synthesis results for approximate adders (AxA) with different bit-width and approximation levels based on a database and simple mathematical operations to reduce the synthesis process complexity during an approximate circuit development. We implement the proposed approach to estimate the synthesis results for the Copy, Error-Tolerant Adder I (ETA-I), Lower-part-or (LOA), and Truncation (Trunc) AxAs. Comparing our estimation with real synthesis results obtained by an industrial synthesis tool, we prove the approach’s efficiency by presenting an average error on the estimated parameters (area, power and delay) less than 10% in the worst case. In addition, our approach reduces by more than 25 times the number of synthesis runs when estimating the synthesis results for all circuits in the bit width range of 2 to 64 with all possible approximation levels.

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Architectural Exploration for Energy-Efficient LMS and NLMS Adaptive Filters VLSI Design

Architectural Exploration for Energy-Efficient LMS and NLMS ...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： Pedro T. L. Pereira Guilherme Paim Eduardo Costa Paulo Flores Sergio Bampi Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil INESC-ID Instituto Superior Técnico ULisboa Portugal

Adaptive filtering plays an essential role in digital signal processing (DSP), being present in many application fields such as noise reduction, telecommunication, and audio signal processing. Notably, the least mean square (LMS) and its normalized version (NLMS) are the most used algorithms due to their simplicity and robustness, which turn them attractive to hardware solutions. This work proposes architectural solutions for LMS and NLMS algorithms targeting an energy-efficient VLSI design. We explore fully sequential, fully parallel, and semi-parallel architectures reusing the hardware as much as possible for both algorithms. It allows for investigating the number of steps necessary for each architecture, demonstrating the energy per operation, circuit area, and throughput savings. The synthesis results highlight the semi-parallel architectures LMS-2 steps and NLMS-3 steps have the best trade-off energy-speed. In addition, we proved the architecture’s energy efficiency in a harmonic canceling case study, achieving more than 60% in energy savings using both filters.

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Jitter Due to Random Telegraph Noise in Voltage-Controlled Oscillators Based on Ring Oscillators

Jitter Due to Random Telegraph Noise in Voltage-Controlled O...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Caroline P. Garcia Bernardo Lourosa Gilson I. Wirth Graduate Program in Microelectronics (PGMicro) Universidade Federal do Rio Grande do Sul Porto Alegre Brazil Electrical Engineering Department (DELET) Universida de Federal do Rio Grande do Sul Porto Alegre Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

As transistors dimensions shrink to nanometer sizes, the variability of their electrical parameters becomes a significant factor in the performance of integrated circuits. Random Telegraph Noise (RTN) is a time-dependent variability that changes the drain current (or threshold voltage) of metal-oxide-semiconductor field-effect transistors (MOSFETs) from one instant in time to the other, leading to jitter in oscillating circuits, such as ring and voltage-controlled (VCO) oscillators. This work evaluates the time-domain jitter caused by the RTN in a capacitive and a current-controlled ring oscillator-based VCO. Different concepts of jitter (absolute jitter, period jitter, and cycle-to-cycle jitter) are studied, focusing on the influence of time window sizes on the jitter amplitude. Monte Carlo simulations are employed for both oscillators, considering a modified SPICE simulator to properly include the RTN impact on the threshold voltage of the transistors.

关键词： Ring oscillators Monte Carlo methods Voltage-controlled oscillators Noise Jitter SPICE Threshold voltage Transistors Autocorrelation Time-domain analysis

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A Multiplier-Less Level-3 Haar Wavelet Transform Approximation Requiring Five Additions Only

A Multiplier-Less Level-3 Haar Wavelet Transform Approximati...

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Proceedings of the IEEE Dallas Circuits and Systems Workshop (DCAS)

作者： Morgana M. A. Da Rosa Guilherme Paim Henrique B. Seidel Sé rgio Almeida Eduardo A. C. Da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing Universidade Cat&#x00F3 lica de Pelotas (UCPel) Brazil Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781665498852

ISBN: (纸本)9781665498869

Approximate transform kernels have emerged as an alternative design to reduce the hardware complexity of digital signal processors by exploiting the intrinsic error resilience of many embedded consumer electronics applications such as signal, image and video processing, and computer vision. The approximate level-4 Haar wavelet transform (AxHWT-4) is the state-of-the-art approximate transform for ECG (electrocardiogram) signal processing and reduces more than nine times the energy consumption compared to the exact transform. In this work, we propose an approximate level-3 Haar wavelet transform (AxHWT-3) for increasing the hardware design efficiency with related to the AxHWT-4 while obtaining higher R-peak detection accuracy in the electrocardiogram signal. Our AxHWT-3 approximation is performed in the Haar matrix kernel to eliminate its multiplications which in the hardware design results in savings of energy consumption and VLSI hardware area. Our AxHWT3 proposal achieves an R-peak detection accuracy of more than 99% and reduces the energy consumption by 15.98 times and the VLSI area by 12.64 times compared to the exact solution (i.e., the original level-3 Haar). In addition, the proposed AxHWT3 outperforms the state-of-the-art AxHWT-4 with a savings of about 32% in power dissipation and 19.5% in VLSI area.

关键词： Wavelet transforms Energy consumption Computer architecture Very large scale integration Electrocardiography Signal processing Hardware

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Towards a Machine Learning Based Method for Indirect Test Generation of Mixed-Signal Circuits

Towards a Machine Learning Based Method for Indirect Test Ge...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Állan F. G. Ferreira Lucas B. Zilch Vinícius Navarro Marcelo S. Lubaszewski Tiago R. Balen Electrical Engineering Department Universidade Federal do Rio Grande do Sul Porto Alegre Brazil Graduate Program in Microelectronics - PGMICRO Universidade Federal do Rio Grande do Sul Porto Alegre Brazil

This work presents the proposal and feasibility evaluation of a machine learning (ML) based method for test generation of analog and mixed-signal circuits. The method first relies on the use of a previously proposed low-cost automatic test generation tool (based on spice simulation) to simulate the circuit specifications and low cost parametric measures (in this case, DC values of circuit nodes under different input stimuli). Variability data, based on Monte Carlo Simulation is also generated by the tool, by using an open source spice simulator and the appropriate foundry models of the transistors. With this dataset in hand, the method consists on training ML models to relate the low cost DC node measurements with the circuit specifications, configuring a well-known indirect test strategy. The models are evaluated and those with the best performance are selected, resulting in a set of low-cost measurements and ML algorithms that represent an indirect test strategy to predict the CUT tested specifications. The considered case study is a fully-differential integrated filter designed on a commercial 180 nm process. Results show a R 2 score equal to 0.76, 0.76 and 0.98 for the DC gain, cutoff frequency and slew rate parameters, respectively. A total of 19 indirect measurements were selected for performing the tests. Finally, the presented method facilitates the implementation of the indirect test in analog circuits. A wide range of design parameters can be explored, selecting those that best contribute to the quality of the indirect test.

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A Power-Efficient FFT Hardware Architecture Exploiting Approximate Adders

A Power-Efficient FFT Hardware Architecture Exploiting Appro...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Guilherme Ferreira Pedro T. L. Pereira Guilherme Paim Eduardo Costa Sergio Bampi Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Brazil Graduate Program in Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil

ISBN: (数字)9781728176703

ISBN: (纸本)9781728176710

This work presents an energy-efficient Fast Fourier Transform (FFT) hardware architecture exploiting approximate adder circuits. The FFT hardware architecture consists of a fixed-point fully sequential architecture with a radix-2 butterfly with decimation in time (DIT). In this paper, we explore a set of approximate adders (LOA, ETA-I, Copy-A, Copy-B, Trunc0, Trunc1) in the butterfly by varying the approximation level (K term). The Root-Mean-Square Error (RMSE) metric shows which approximate level term allows the FFT processing without widely signal losses. The results show that our best-proposed FFT employing Trunc0 approximate adder with K =10 saves up to 35% of power dissipation compared to the FFT with the original radix-2 butterfly using the synthesis tool operators.

关键词： Measurement Fast Fourier transforms Circuits and systems Hardware Energy efficiency Topology Power dissipation

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Boosting the Efficiency of the Harmonics Elimination VLSI Architecture by Arithmetic Approximations

Boosting the Efficiency of the Harmonics Elimination VLSI Ar...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Patricia da Costa Pedro T. L. Pereira Guilherme Paim Eduardo da Costa Sergio Bampi Graduate Program in Microelectronics (PGMICRO) - Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program in Electronic Engineering and Computing - Catholic University of Pelotas (UCPel) Pelotas Brazil

Approximate computing emerged as a key alternative for trading off accuracy against energy efficiency and area reduction. Error-tolerant applications, such as multimedia processing, machine learning, and signal processing, can process the information with lower-than-standard accuracy at the circuit level while still fulfilling a good and acceptable service quality at the application level. Adaptive filtering-based systems have been demonstrating high resiliency against hardware errors due to their intrinsic self-healing characteristic. This paper investigates the design space exploration of arithmetic approximations in a Very Large-Scale Integration (VLSI) harmonic elimination (HE) hardware architecture based on Least Mean Square (LMS) adaptive filters. We evaluate the Pareto front of the area- and power versus quality curves by relaxing the arithmetic precision and by adopting both approximate multipliers (AxMs) in combination with approximate adders (AxAs). This paper explores the benefits and impacts of the Dynamic Range Unbiased (DRUM), Rounding-based Approximate (RoBA), and Leading one Bit-based Approximate (LoBA) multipliers in the power dissipation, circuit area, and quality of the VLSI HE architectures. Our results highlight the LoBA 0 as the most efficient AxM applied in the HE architecture. We combine the LoBA 0 with Copy and LOA AxAs with variations in the approximation level (L). Notably, LoBA 0 and LOA with $L=6$ resulted in savings of 43.7% in circuit area and 45.2% in power dissipation, compared to the exact HE, which uses multiplier and adder automatically selected by the logic synthesis tool. Finally, we demonstrate that the best hardware architecture found in our investigation successfully eliminates the contaminating spurious noise (i.e., 60 Hz and its harmonics) from the signal.

关键词： Power quality Computer architecture Very large scale integration Harmonic analysis Boosting Hardware Power dissipation

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Characterization of Enclosed Layout Transistors for Analog Applications on a130nm Technology

Characterization of Enclosed Layout Transistors for Analog A...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Gustavo P. Platcheck Guilherme S. Cardoso Tiago R. Balen Graduate Program on Microelectronics-PGMICRO UFRGS Porto Alegre Brazil Department of Electronic IFSul Pelotas Brazil

ISBN: (数字)9781728196251

ISBN: (纸本)9781728196268

Enclosed Layout Transistors (ELT) comprise a feasible design alternative to hardening CMOS circuits against total ionizing dose effects. This design technique significantly reduces the leakage paths produced by trapped charges in the field oxide of regular NMOS devices. This work presents the characterization of several ELT devices designed and fabricated on a 130nm technology aiming at analog applications. Standard (rectangular) transistors with equivalent aspect ratio were also considered for comparison. The experimental data are compared with simulations performed using a commercial design tool, considering the aspect ratio (W/L) extracted from the layout. ELTs with the drain designed both as the inner and outer terminal were characterized and compared. Additionally, in order to improve the achievable aspect ratio range of the square ELTs, parallel and series associations of enclosed devices were implemented as well. According to obtained results, there may be significant differences between the W/L extracted from the design tool and its actual value in the fabricated device. For all enclosed devices, the simulation overestimates the current values. A different pattern regarding the influence of drain location (inner or outer terminal) on current performance is also observed when comparing measured data with simulations. Additionally, associations of ELT showed to be feasible to widen the range of possible aspect ratio of this particular transistor.

关键词： Transistors Mathematical model Logic gates Layout Data models Performance evaluation Tools

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Low-Voltage Dynamic Comparator with Bulk-Driven Floating Inverter Amplifier

Low-Voltage Dynamic Comparator with Bulk-Driven Floating Inv...

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Bruno Canal Hamilton D. Klimach Sergio Bampi Tiago R. Balen PGMicro - Graduate Program on Microelectronics Federal University of Rio Grande do Sul Porto Alegre RS Brazil

ISBN: (数字)9781728196251

ISBN: (纸本)9781728196268

This work presents a low voltage dynamic comparator for low-power ADC applications. The dynamic comparator uses a pre-amplifier powered by a floating reservoir capacitor and bulk-driven structure. The latch stage is done by a simple circuit to reduce the total voltage overhead necessary to define the logic levels and uses a charge sharing technique in order to reduce the energy consumption per conversion. The floating reservoir capacitor powered pre-amplifier reduces the impacts of global process variability and improves the input common-mode voltage performance. The bulk-driven structure lowers the threshold voltages of the pre-amplifier transistors at the sampling phase. Such structure also works as a positive feedback signal during the comparison phase to provide extra transconductance. The proposed dynamic comparator is designed and simulated in 28nm CMOS technology and reaches a performance suitable for 8 bits ADCs working with 600mV power supply. The dynamic comparator achieves 380μV input-referred noise, while consuming only 40 fJ per comparison and having a nominal delay of 2.26ns.

关键词： Latches Inverters Transistors Topology Transconductance Capacitors Reservoirs

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Optimizing Iterative-based Dividers for an Efficient Natural Logarithm Operator Design

Optimizing Iterative-based Dividers for an Efficient Natural...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Patrícia Ücker Miguel R. Weirich Guilherme Paim Eduardo A. C. da Costa Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

This work proposes to optimize iterative-based dividers for a natural logarithm operator design. The logarithm operator approximates the function at the base e. Such an operator is implemented using Taylor Series approximation. In this approximation, the division is a costly operation. In this work, we explore two iterative-based divider circuits for logarithm operator. We also offer an algorithm responsible for allowing input values different from the ones in the convergence region of the Taylor Series, with a reduced number of iterations. Through co-simulation using both the Matlab ® and ModelSim ® softwares, it was possible to determine the approximation quality of the implemented circuits, with a curve response very close to the Matlab one. Moreover, the Goldschmidt divider presents a slightly fewer relative error, mainly for higher input values comparing with Newton-Raphson. Synthesis results show that although the logarithm circuit with Newton-Raphson divider has marginally more area, it is more power-efficient than the one using Goldschmidt divider.

关键词： Approximation algorithms Taylor series Mathematical model Newton method Convergence Hardware Matlab

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