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检索条件"机构=Graduate Program on Microelectronics-UFRGS"

共 72 条记录，以下是31-40 订阅

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Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture

Optimizing the Montgomery Modular Multiplier for a Power- an...

引用

Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Mateus Terribele Leme Guilherme Paim Leandro M. G Rocha Patricia Ücker Vitor G. Lima Rafael Soares Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Graduate Program on Computer Science (PPGC) Federal University of Pelotas (UFPel)

ISBN: (数字)9781728180588

ISBN: (纸本)9781728180595

Cryptography hardware design is a key challenge towards the confidentiality advance in the prominent field of the internet of things (IoT). The rise of IoT embedded devices boosts the demand for power- and area- efficient solutions for cryptography hardware. The higher the robustness of the cryptography algorithm is, the higher are the hardware complexity, the circuit area, and energy consumption. Asymmetric algorithms are a particular class widely employed in ultra-secure cryptosystems. The high time-hardness to break the private-key in asymmetric algorithms is a result of its high mathematical complexity. RSA is an asymmetric algorithm that performs successive modular multiplications to encrypt and de-encrypt the information. Therefore, arithmetic operators are the most significant part regarding circuit area and power dissipation. This work evaluates a design space exploration for power- and area-efficient hardware VLSI design in the modular Montgomery multiplier employed in the RSA algorithm.

关键词： Hardware Computer architecture Adders Power dissipation Public key Very large scale integration

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Two-transistor voltage-measurement-based test structure for fast extraction of MOS mismatch design parameters 32

Two-transistor voltage-measurement-based test structure for ...

引用

32nd IEEE International Conference on Microelectronic Test Structures, ICMTS 2019

作者： Brito, Juan Pablo Martinez Bampi, Sergio Graduate Program on Microelectronics - PGMICRO Federal University of Rio Grande Do sul - UFRGS Brazil CEITEC S.A. Semiconductors Porto Alegre Brazil

ISBN: (纸本)9781728114668

This paper proposes a new test structure and a measurement method for measuring MOS transistors mismatches. The structure is based on the combination of two stacked MOS transistors and the measurement methodology relies on two single DC voltage measurements. The method allows to extract separately σ(δ VTH) and σ(Δβ/β) and enables fast extraction of design MOS mismatch parameters such as AVTH and Aβ with less than 2% error. The simple data post-processing algorithm results in an increase of 30x in the measurement speed with data correlation coefficient not less than 0.94 (R2≥0.94). Rapid address decoding and bias configuration have been used in order to select each device in a two-dimensional (2D) DUT matrix of FETs. The experimental data presented herein for analysis is taken from measurements in a prototype fabricated in 65nm CMOS bulk process. © 2019 IEEE.

关键词： Voltage measurement

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Approximate SATD Hardware Accelerator Using the 8 × 8 Hadamard Transform

Approximate SATD Hardware Accelerator Using the 8 × 8 Hadam...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Matheus F. Stigger Victor H. S. Lima Leonardo B. Soares Claudio M. Diniz Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Federal Institute of Rio Grande do Sul (IFRS) Rio Grande Brazil Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

Sum of Absolute Transformed Differences (SATD) is a distortion metric based on the Hadamard Transform. It is used in current video encoders inside the refinement stage of motion estimation, which decides the best block of pixels to be used as prediction for each block to be encoded. To reduce the computational effort incurred by the SATD calculation, this work proposes an approximate SATD hardware accelerator by excluding columns of adders/subtractors of the 8 × 8 Hadamard Transform (HT). The proposed approximate accelerator reduces energy by up to 40.78% compared to the precise SATD accelerator.

关键词： Transforms Computer architecture Hardware Video coding Adders Registers Software

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VLSI Design of Tree-Based Inference for Low-Power Learning Applications

VLSI Design of Tree-Based Inference for Low-Power Learning A...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Brunno A. Abreu Mateus Grellert Sergio Bampi Graduate Program in Microelectronics (PGMICRO) INF-UFRGS Federal University of Rio Grande do Sul Porto Alegre Brazil Department of Informatics and Statistics − INE Federal University of Santa Catarina (UFSC) Florianópolis Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

The use of Machine Learning techniques in battery-powered devices has increased in recent years. Therefore, evaluating power-accuracy trade-offs of inference models has become important. This work explores decision trees architectures, analyzing the effects of model complexity and approximation in power and accuracy. By quantizing the inputs to limited widths, we increased the accuracy of the models in up to 8.7% compared to precise cases. In terms of power, the variation in model complexity was more significant than in input width, as we obtained reductions of up to 97% by decreasing the tree depth, compared to 88% when decreasing the width.

关键词： Complexity theory Hardware Integrated circuit modeling Training Analytical models Decision trees Quantization (signal)

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Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors

Maximizing the Power-Efficiency of the Approximate Pruned Mo...

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IEEE International New Circuits and Systems Conference

作者： Guilherme Paim Leandro M. G. Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil

This paper proposes the use of approximate adder compressors for a low-power 8-point Modified Rounded Discrete Cosine Transform (MRDCT_(10)) implementation. The algebraic approximation of the MRDCT was previously introduced in the literature, whose resultant matrix is only composed of 0, 1 and -1 values. Therefore, the MRDCT can be efficiently implemented using only adders and subtractors. We present an environment for the synthesis of the MRDCT in Cadence Encounter RTL Compiler tool. The synthesis reports are based on a set of real images as input vectors to obtain valid power results. Our results show that the use of approximate adder/subtractor compressors in hardwired state-of-the-art 8-point approximate MRDCT_(10) achieves savings ranging from 26% to 52.54% when compared with the macro function (+) from the tool.

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Exploring Architectural Solutions for an Energy-Efficient Kalman Filter Gain Realization

Exploring Architectural Solutions for an Energy-Efficient Ka...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Pedro T. L. Pereira Guilherme Paim Patrícia Ücker Eduardo Costa Sérgio Almeida Sergio Bampi Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil

The Kalman filter is a signal processing algorithm that plays an essential role in real-time mobile applications as nano drones navigation, spacecraft orbit control, GPS positioning, image recognition, and sensor data fusion for wearable health monitoring. However, the Kalman filter is a compute-intensive kernel since it implements a high amount of complex matrix operations like multiplications and inversions. The most timing-consuming tasks of the Kalman filter is the Kalman gain. Therefore, this work presents four architectural solutions to explore real-time and energy-efficient Kalman gain processing.

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Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation

Exploring Motion Vector Cost with Partial Distortion Elimina...

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IEEE International New Circuits and Systems Conference

作者： Brunno Abreu Mateus Grellert Guilherme Paim Thomas Fontanari Leandro M. G. Rocha Eduardo A. C. da Costa Sergio Bampi Graduate Program in Microelectronics Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil Graduate Program in Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil

Integer Motion Estimation (IME) is one of the most costly steps in the video coding process, being responsible for 60% of the total encoding time. Two parameters are considered when calculating the redundancies (distortion) between video blocks: Sum of Absolute Differences (SAD) and motion vector cost (MV_(cost)). Partial Distortion Elimination (PDE) techniques may be used to optimize the calculation of the SAD unit itself, in order to avoid the computation of candidates that will certainly not be selected in the IME. This paper proposes an optimization in the distortion calculation by taking advantage of the PDE technique in SAD operation by including MVcost, in order to save even more cycles when compared to standard PDE usage, considering the High Efficiency Video Coding (HEVC) standard. We found out that the inclusion of MV_(cost) in the distortion cost achieves a quality increase of up to 1.28%. We compare three versions: adding MV_(cost) before/after SAD using a multiplexer, and before SAD with a Carry-Save Adder (CSA). The use of PDE including MV_(cost) before SAD calculation using a multiplexer achieves an average reduction of 17.5% in the energy consumption when compared to accumulating MV_(cost) after SAD. When using the CSA, we obtain an additional average reduction of 1.94%.

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A 0.6 V Current Reference Based on the MOSFET Forward-Body-Biased ZTC Condition

A 0.6 V Current Reference Based on the MOSFET Forward-Body-B...

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IEEE International Conference on Electronics, Circuits and Systems

作者： Luis Henrique Rodovalho Pedro Toledo Sergio Bampi Integrated Circuits Laboratory Federal University of Santa Catarina Brazil Politecnico di Torino - Polito Turin Italy Graduate Program on Microelectronics - UFRGS Porto Alegre RS Brazil

This work presents a self biased current reference circuit based on the MOSFET Zero Temperature Coefficient (ZTC) condition. To achieve lower supply voltage (V_(DD)) operation, the proposed circuit employs forward body biasing technique to decrease the MOSFET ZTC biasing point. In addition, a body-driven pseudo differential Operational Transconductance Amplifier (OTA) is used to further reduce the minimum supply voltage. From transitor-level simulations, the current reference is predicted to have an Effective Temperature Coefficient (TC_(eff)) of 65 ppm/℃ from -55 to 125℃ and a fabrication sensitivity of σ/μ = 6.5%, including process and mismatch variability. The power supply sensitivity is around 0.75%/V for this new reference.

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A Configurable Pruning Gaussian Image Filter for Energy-Efficient Edge Detection

A Configurable Pruning Gaussian Image Filter for Energy-Effi...

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IEEE International Conference on Electronics, Circuits and Systems

作者： Leonardo Bandeira Soares Eduardo Antonio Cesar da Costa Sergio Bampi Federal Institute of Technology of Rio Grande do Sul (IFRS) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Pelotas Brazil Graduate Program on Microelectronics Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

This paper presents a new configurable pruning Gaussian image filter CMOS architecture to address energy efficiency requirements regarding edge detection applications. Low-energy consumption is key for Internet of Things (IoT) devices. Many emerging IoT applications rely on cameras to extract video or image features by running power-hungry computer vision algorithms. The Gaussian image filter is one of the most compute intensive tasks for pre-processing edge detection techniques which are widely adopted in the computer vision domain. Therefore, our proposed 2D Gaussian filter architecture enables: i) a low power and low area overhead runtime configuration scheme based on clock gating technique to prune the Gaussian filter (GF) window size, and ii) run-time capability to balance the tradeoff between edge detection quality and energy efficiency. Our proposed configurable architecture is synthesized and mapped onto 45 nm technology for an ASIC implementation. Results show that for 6 different run-time profiles our proposed configurable architecture provides power dissipation reduction of up to 64% with multiple levels of edge detection quality, which is assessed by considering the performance conformance metric.

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Approximate Sum of Absolute Transformed Differences Hardware Accelerator

Approximate Sum of Absolute Transformed Differences Hardware...

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IEEE International Conference on Electronics, Circuits and Systems

Motion Estimation and mode decision are the most compute-intensive tasks in recent video encoders. Sum of Absolute Transformed Differences (SATD) is a distortion metric used inside ME and mode decision to decide the best block to be used as prediction for each block to be encoded. To reduce the complexity of SATD calculation, this work proposes an approximate SATD hardware accelerator based on 1D 4 × 4 Hadamard Transform, in contrast with the precise SATD hardware accelerator that contains a 2D 4 × 4 Hadamard Transform. The proposed approximate SATD accelerator reduces power dissipation in 66.86% compared to the precise SATD accelerator while increasing BD-BR only by less than 0.748%, which is a better result than SAD accelerator that increases BD-BR in up to 0.830% compared to precise SATD.

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