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Conferences in Research and Practice in Information Technology Series 2011年 118卷 33-34页

作者： Perrin, Dimitri Ohsaki, Hiroyuki Centre for Scientific Computing and Complex Systems Modelling Dublin City University Dublin Ireland Information Sharing Platform Laboratory Department of Information Networking Graduate School of Information Science and Technology Osaka University 1-5 Yamadaoka Suita Osaka 565-0871 Japan

ISBN: (纸本)9781920682989

Understanding the dynamics of disease spread is essential in contexts such as estimating load on medical services, as well as risk assessment and intervention policies against large-scale epidemic outbreaks. However, most of the information is available after the outbreak itself, and preemptive assessment is far from trivial. Here, we report on an agent-based model developed to investigate such epidemic events in a stylised urban environment. For most diseases, infection of a new individual may occur from casual contact in crowds as well as from repeated interactions with social partners such as work colleagues or family members. Our model therefore accounts for these two phenomena. Given the scale of the system, efficient parallel computing is required. In this presentation, we focus on aspects related to paralllelisation for large networks generation and massively multi-agent simulations. © 2011, Australian Computer Society, Inc.

关键词： Complex networks

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Software Quality Assurance Methodologies and Techniques

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Advances in Software Engineering 2012年第1期2012卷

作者： Chin-Yu Huang Hareton Leung Wu-Hon Francis Leung Osamu Mizuno Department of Computer Science and Institute of Information Systems and Applications National Tsing Hua University Hsinchu 30013 Taiwannthu.edu.tw Department of Computing Hong Kong Polytechnic University Kowloon Hong Kongpolyu.edu.hk Department of Computer Science Illinois Institute of Technology Chicago IL 60616 USAiit.edu Graduate School of Science and Technology Kyoto Institute of Technology Kyoto 606-8585 Japankit.ac.jp

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Design and implementation of communication system of the Dawning 6000 supercomputer

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中国计算机科学前沿 2010年第4期4卷 466-474页

作者： Qiang LI Bo LI Zhigang HUO Ninghui SUN National Research Center for Intelligent Computing Systems Beijing 100190China Key Laboratory of Computer System and Architecture Chinese Academy of SciencesBeijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China National Research Center for Intelligent Computing Systems Beijing 100190China Key Laboratory of Computer System and Architecture Chinese Academy of SciencesBeijing 100190China

An increasing number of supercomputers adopt a heterogeneous architecture, consisting of both general purpose CPUs and specialized accelerators. Such design is beneficial for scalability and power, but on the other hand, heterogeneity brings new challenges in communication systems to connect heterogeneous components and provide support for programming. The communication system of the Dawning 6000 connectstwo kinds of heterogeneous processors, Loongson and AMD, and adopts a three layer architecture with an intranode layer between heterogeneous components. To efficiently connect heterogeneous components, the system forms a global address space and provides a mechanism for message transmission via an in-node global store; and employing Infiniband network, provides an OS-bypassing virtualization method to share an Infiniband card between nodes. To facilitate programming on heterogeneous processors, it supports unified parallel C (UPC), with a modified complier based on global address space. Also, aspecial collective network is implemented for collective operations. Results obtained from a prototype system prove these features to be both feasible and efficient.

关键词： hyper parallel processing (HPP) global address space (GAS) virtualization Dawning 6000 unified parallel C (UPC)

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Cool mega-array: A highly energy efficient reconfigurable accelerator

Cool mega-array: A highly energy efficient reconfigurable ac...

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2011 International Conference on Field-Programmable Technology, FPT 2011

作者： Ozaki, N. Yoshihiro, Y. Saito, Y. Ikebuchi, D. Kimura, M. Amano, H. Nakamura, H. Usami, K. Namiki, M. Kondo, M. Department of Information and Computer Science Keio University 3-14-1 Hiyoshi Yokohama 223-8522 Japan Department of Information Physics and Computing University of Tokyo 7-3-1 Hongo Bunkyo-ku Tokyo 113-8656 Japan Department of Information Science and Engineering Shibaura Institute of Technology 3-7-5 Toyosu Kohtoh-ku Tokyo 135-8548 Japan Dpartment of Computer and Information Science Tokyo University of Agriculture and Technology 2-24-16 Nakamachi Koganei Tokyo 184-8588 Japan Graduate School of Information Systems Tokyo University of Electro-Communication 1-5-1 Chofugaoka Chofu Tokyo 182-8585 Japan

ISBN: (纸本)9781457717406

A highly energy efficient reconfigurable accelerator called CMA (Cool Mega-Array) is proposed. It consists of a large Processing Element (PE) array without memory elements for maintain result of ALU and configuration data, a small simple programmable micro controller for data management, and the data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware context switching, storing intermediate data in registers, and clock distribution for them are eliminated from PE array which occupies large area of a chip. Configuration registers are collected to small area of micro controller. The data flow graph mapped on the PE array is static during execution. Various application programs can be implemented by making the best use of flexible data management instructions with the micro controller. When the delay time in the PE array is longer than the data handling time with the micro controller, the supply voltage for the PE array is scaled to reduce the power consumption without degrading the performance. In the opposite case, wave pipelining is applied to enhance PE array performance. A prototype chip CMA-1 with 8 × 8 PE array with 24-bit data width was fabricated in 2.1 × 4.2mm2 65-nm CMOS technology, and achieves 2.4-GOPS/11.2-mW sustained performance. This energy efficiency is comparable to that of the most energy efficient accelerators that have been reported. © 2011 IEEE.

关键词： Electric power utilization

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Cool Mega-Array: A highly energy efficient reconfigurable accelerator

Cool Mega-Array: A highly energy efficient reconfigurable ac...

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： N. Ozaki Y. Yoshihiro Y. Saito D. Ikebuchi M. Kimura H. Amano H. Nakamura K. Usami M. Namiki M. Kondo Department of Information and Computer Science Keio University Yokohama Japan Department of Information Physics and Computing University of Tokyo Bunkyo Tokyo Japan Department of Information Science and Engineering Shibaura Institute of Technology Kohtoh Tokyo Japan Department of Computer and Information Science Tokyo University of Agriculture and Technology Koganei Tokyo Japan Graduate School of Information Systems Tokyo University of Electro-Communication Chofu Tokyo Japan

A highly energy efficient reconfigurable accelerator called CMA (Cool Mega-Array) is proposed. It consists of a large Processing Element (PE) array without memory elements for maintain result of ALU and configuration data, a small simple programmable micro controller for data management, and the data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware context switching, storing intermediate data in registers, and clock distribution for them are eliminated from PE array which occupies large area of a chip. Configuration registers are collected to small area of micro controller. The data flow graph mapped on the PE array is static during execution. Various application programs can be implemented by making the best use of flexible data management instructions with the micro controller. When the delay time in the PE array is longer than the data handling time with the micro controller, the supply voltage for the PE array is scaled to reduce the power consumption without degrading the performance. In the opposite case, wave pipelining is applied to enhance PE array performance. A prototype chip CMA-1 with 8 × 8 PE array with 24-bit data width was fabricated in 2.1 × 4.2mm 2 65-nm CMOS technology, and achieves 2.4-GOPS/11.2-mW sustained performance. This energy efficiency is comparable to that of the most energy efficient accelerators that have been reported.

关键词： Arrays Registers Clocks Delay Context Leakage current

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Exploiting data deduplication to accelerate live virtual machine migration

Exploiting data deduplication to accelerate live virtual mac...

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作者： Zhang, Xiang Huo, Zhigang Ma, Jie Meng, Dan National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100049 China

ISBN: (纸本)9780769542201

As one of the key characteristics of virtualization, live virtual machine (VM) migration provides great benefits for load balancing, power management, fault tolerance and other system maintenance issues in modern clusters and data centers. Although Pre-Copy is a widespread used migration algorithm, it does transfer a lot of duplicated memory imagedata from source to destination, which results in longer migration time and downtime. This paper proposes a novel VM migration approach, named Migration with Data Deduplication (MDD), which introduces data deduplication into migration. MDD utilizes the self-similarity of run-time memory image, uses hash based fingerprints to find identical and similar memory pages, and employs Run Length Encode (RLE) to eliminate redundant memory data during migration. Experiment demonstrates that compared with Xen's default Pre- Copy migration algorithm, MDD can reduce 56.60% of total data transferred during migration, 34.93% of total migration time, and 26.16% of downtime on average. © 2010 IEEE.

关键词： Virtualization

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Managing continuations for proper tail recursion

Managing continuations for proper tail recursion

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2010 International Conference on Lisp, ILC '10

作者： Yasugi, Masahiro Komiya, Tsuneyasu Hiraishi, Tasuku Umatani, Seiji Graduate School of Informatics Kyoto University Japan Graduate School of Information Systems University of Electro-Communications Japan Academic Center for Computing and Media Studies Kyoto University Japan

ISBN: (纸本)9781450304702

Implementations of Scheme are required to be properly tail-recursive and to support an unbounded number of active tail calls. Clinger proposed a formal definition of proper tail recursion based on space efficiency. This definition encompasses systematic tail call optimization, where every tail call is converted to a jump (with an optional trampoline), as well as Baker's implementation of Scheme in the C language with CPS (continuation-passing style) conversion. Baker's implementation is space-efficient, since no new continuation is created on a CPS-converted tail call and garbage is collected even on C's execution stack. In our work, we discovered that an abstract machine that runs CPS-converted programs cannot be considered properly tail-recursive according to Clinger's definition if continuation closures are simply created with the lexical environments for all variables. Furthermore, an abstract machine that employs neither explicit environments nor continuations is also improperly tail-recursive. This paper discusses the above issue and also proposes new techniques to implement a properly tail-recursive Scheme interpreter in an extended C language by following space-efficiency-based definitions of proper tail recursion. In our approach, a program is not converted into CPS. The primary concept is to avoid stack overflow by creating a space-efficient first-class continuation represented as a list containing only the "Frame" objects necessary for the rest of the computation and immediately invoking the continuation. We use a language mechanism called "L-closures" to access the contents of the execution stack as values of legal data structures and variables for implementing garbage collection and capturing continuations. © 2010 ACM.

关键词： Efficiency

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Mining learners' disorientation in Web-based learning

Mining learners' disorientation in Web-based learning

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18th International Conference on Computers in Education, ICCE 2010

作者： Shih, Yu-Cheng Hsu, Yung-Chi Chen, Sherry Y. Graduate Institute of Network Learning Technology National Central University Taiwan Department of Information Systems and Computing Brunel University United Kingdom

ISBN: (纸本)9789834251246

Web-based learning systems provide flexible ways for learners to develop their own learning strategies. However, some learners may experience more disorientation problems when they need to decide the learning strategies by themselves. In other words, not all of learners are suitable to use the Web-based learning systems. Therefore, it is necessary to investigate how learners' individual differences influence their disorientation problems. To this end, this study addresses this issue. Unlike other previous studies, we will not only examine how learners' individual differences influence their disorientation but also investigate how the learners' disorientation influences their learning performance. The other novelty of this study is the fact that we use a data mining approach to conduct data analyses. The results indicate that learners' computer experience is a major factor to influence their disorientation. Moreover, their disorientation may also influence their learning performance. The results are useful for developing Web-based learning systems to reduce learners' disorientation.

关键词： Data mining

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Parallel matrix-matrix multiplication based on HPL with a GPU-accelerated PC cluster

Parallel matrix-matrix multiplication based on HPL with a GP...

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International Conference on Networking and computing

作者： Wang, Qin Ohmura, Junichi Axida, Shan Miyoshi, Takefumi Irie, Hidetsugu Yoshinaga, Tsutomu University of Electro-Communications Graduate School of Information Systems Department of Information Network Systems Laboratory for Network Computing 1-5-1 Chofugaoka Chofu-shi 182-8585 Tokyo Japan

ISBN: (纸本)9780769542775

In this paper, we propose an approach for significantly improving the performance of parallel matrix-matrix multiplication using a GPU-accelerated cluster. For one node, we implement a CPUs-GPU parallel double-precision general matrix-matrix multiplication (dgemm) operation and achieve a performance improvement of 32% as compared to the GPU-only case and 56% as compared to the CPUs-only case. For the entire cluster, we use the overlap GPU acceleration solution to high-performance Linpack (HPL), which eliminates the close dependency between the LU decomposition and the dgemm operation, and achieve a performance improvement of 17% as compared to the flat GPU acceleration case. © 2010 IEEE.

关键词： Program processors

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Replication-based highly available metadata management for cluster file systems

Replication-based highly available metadata management for c...

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作者： Chen, Zhuan Xiong, Jin Meng, Dan National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences China Department of Computer Science University of Rochester United States

ISBN: (纸本)9780769542201

In cluster file systems, the metadata management is critical to the whole system. Past researches mainly focus on journaling which alone is not enough to provide high-available metadata service. Some others try to use replication, but the extra latency accompanied is a main problem. To guarantee both availability and efficiency, we propose a mechanism for building highly available metadata servers based on replication, which integrates Paxos algorithm effectively into metadata service. The Packed Multi-Paxos is proposed to reduce the latency brought by replication, which is self-adaptive and can make the replication to achieve high throughput under heavy client load and low latency under light client load. By designing efficient architecture and coordination mechanism, all replica server nodes simultaneously provide metadata read-access service. This high-available mechanism could decrease the impact of server failures and there is no interruption of service. The performance results show that the latency caused by replication and redundancy is well under control, and the performance of metadata read operation gains improvement. © 2010 IEEE.

关键词： Metadata

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