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arXiv 2021年

作者： Huang, Hong Song, Yu Wu, Yao Shi, Jia Xie, Xia Jin, Hai National Engineering Research Center for Big Data Technology Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

Link prediction and node classification are two important downstream tasks of network representation learning. Existing methods have achieved acceptable results but they perform these two tasks separately, which requires a lot of duplication of work and ignores the correlations between tasks. Besides, conventional models suffer from the identical treatment of information of multiple views, thus they fail to learn robust representation for downstream tasks. To this end, we tackle link prediction and node classification problems simultaneously via multi-task multi-view learning in this paper. We first explain the feasibility and advantages of multi-task multi-view learning for these two tasks. Then we propose a novel model named as MT-MVGCN to perform link prediction and node classification tasks simultaneously. More specifically, we design a multi-view graph convolutional network to extract abundant information of multiple views in a network, which is shared by different tasks. We further apply two attention mechanisms: view attention mechanism and task attention mechanism to make views and tasks adjust the view fusion process. Moreover, view reconstruction can be introduced as an auxiliary task to boost the performance of the proposed model. Experiments on real-world network datasets demonstrate that our model is efficient yet effective, and outperforms advanced baselines in these two tasks. © 2021, CC BY.

关键词： Data mining

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Superpage-Friendly Page Table Design for Hybrid Memory Systems 6th

Superpage-Friendly Page Table Design for Hybrid Memory Syste...

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6th International Conference of Pioneering Computer Scientists, Engineers and Educators, ICPCSEE 2020

作者： Wang, Xiaoyuan Liu, Haikun Liao, Xiaofei Jin, Hai National Engineering Research Center for Big Data Technology and System Huazhong University of Science and Technology Wuhan430074 China Service Computing Technology and System Lab Huazhong University of Science and Technology Wuhan430074 China Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan430074 China School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9789811579806

Page migration has long been adopted in hybrid memory systems comprising dynamic random access memory (DRAM) and non-volatile memories (NVMs), to improve the system performance and energy efficiency. However, page migration introduces some side effects, such as more translation lookaside buffer (TLB) misses, breaking memory contiguity, and extra memory accesses due to page table updating. In this paper, we propose superpage-friendly page table called SuperPT to reduce the performance overhead of serving TLB misses. By leveraging a virtual hashed page table and a hybrid DRAM allocator, SuperPT performs address translations in a flexible and efficient way while still remaining the contiguity within the migrated pages. © 2020, Springer Nature Singapore Pte Ltd.

关键词： Energy efficiency

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GradSA: Gradient Sparsification and Accumulation for Communication-Efficient Distributed Deep Learning 15th

GradSA: Gradient Sparsification and Accumulation for Communi...

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15th International Conference on Green, Pervasive, and Cloud computing, GPC 2020

作者： Liu, Bo Jiang, Wenbin Zhao, Shaofeng Jin, Hai He, Bingsheng National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab Huazhong University of Science and Technology Wuhan China Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System Engineering Research Center of Data Storage Systems and Technology Huazhong University of Science and Technology Wuhan China Library Henan University of Economics and Law Zhengzhou China Department of Computer Science School of Computing National University of Singapore Singapore Singapore

ISBN: (纸本)9783030642426

Large-scale distributed deep learning is of great importance in various applications. For distributed training, the inter-node gradient communication often becomes the performance bottleneck. Gradient sparsification has been proposed to reduce the communication overhead. However, the sparsification only arbitrarily selects a small fraction of gradients, while the efficiency of selection dimension has been overlooked. Furthermore, gradient staleness is inevitable after applying the sparsification which will ultimately lead to model divergence. In this paper, we propose a staleness-compensated sparse stochastic gradient descent algorithm, GradSA, to improve the training efficiency. Layer-level gradients are sparsified to reduce the communication overhead, which conform to the characteristics of the network structure, and historical accumulation of the approximated gradients is utilized to speed up convergence. We demonstrate the model convergence acceleration and the efficiency of our layer-level selection over existing state-of-the-art works, such as DGC, TernGrad, and 8-Bit quantization. © 2020, Springer Nature Switzerland AG.

关键词： Efficiency

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Spara: An Energy-Efficient ReRAM-Based Accelerator for Sparse Graph Analytics Applications

Spara: An Energy-Efficient ReRAM-Based Accelerator for Spars...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Long Zheng Jieshan Zhao Yu Huang Qinggang Wang Zhen Zeng Jingling Xue Xiaofei Liao Hai Jin National Engineering Research Center for Big Data Technology and System/Service Computing Technology and System Lab/Cluster and Grid Computing Lab Huazhong University of Science and Technology China UNSW Sydney Australia

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168777

Resistive random access memory (ReRAM) addresses the high memory bandwidth requirement challenge of graph analytics by integrating the computing logic in the memory. Due to the matrix-structured crossbar architecture, existing ReRAM-based accelerators, when handling real-world graphs that often have the skewed degree distribution, suffer from the severe sparsity problem arising from zero fillings and activation nondeterminism, incurring substantial ineffectual *** this paper, we observe that the sparsity sources lie in the consecutive mapping of source and destination vertex index onto the wordline and bitline of a crossbar. Although exhaustive graph reordering improves the sparsity-induced inefficiency, its totally-random (source and destination) vertex mapping leads to expensive overheads. This work exploits the insight in a mid-point vertex mapping with the random wordlines and consecutive bitlines. A cost-effective preprocessing is proposed to exploit the insight by rapidly exploring the crossbar-fit vertex reorderings but ignores the sparsity arising from activation dynamics. We present a novel ReRAM-based graph analytics accelerator, named Spara, which can maximize the workload density of crossbars dynamically by using a tightly-coupled bank parallel architecture further proposed. Results on real-world and synthesized graphs show that Spara outperforms GraphR and GraphSAR by 8.21 × and 5.01 × in terms of performance, and by 8.97 × and 5.68× in terms of energy savings (on average), while incurring a reasonable (

关键词： Indexes Electrodes Random access memory Parallel architectures Resistance Memory management

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A Heterogeneous PIM Hardware-Software Co-Design for Energy-Efficient Graph Processing

A Heterogeneous PIM Hardware-Software Co-Design for Energy-E...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Yu Huang Long Zheng Pengcheng Yao Jieshan Zhao Xiaofei Liao Hai Jin Jingling Xue National Engineering Research Center for Big Data Technology and System/Service Computing Technology and System Lab/Cluster and Grid Computing Lab Huazhong University of Science and Technology China UNSW Sydney Australia

ISBN: (数字)9781728168760

ISBN: (纸本)9781728168777

Processing-In-Memory (PIM) is an emerging technology that addresses the memory bottleneck of graph processing. In general, analog memristor-based PIM promises high parallelism provided that the underlying matrix-structured crossbar can be fully utilized while digital CMOS-based PIM has a faster single-edge execution but its parallelism can be low. In this paper, we observe that there is no absolute winner between these two representative PIM technologies for graph applications, which often exhibit irregular workloads. To reap the best of both worlds, we introduce a new heterogeneous PIM hardware, called Hetraph, to facilitate energy-efficient graph processing. Hetraph incorporates memristor-based analog computation units (for high-parallelism computing) and CMOS-based digital computation cores (for efficient computing) on the same logic layer of a 3D die-stacked memory device. To maximize the hardware utilization, our software design offers a hardware heterogeneity-aware execution model and a workload offloading mechanism. For performance speedups, such a hardware-software co-design outperforms the state-of-the-art by 7.54 ×(CPU), 1.56 ×(GPU), 4.13× (memristor-based PIM) and 3.05× (CMOS-based PIM), on average. For energy savings, Hetraph reduces the energy consumption by 57.58× (CPU), 19.93× (GPU), 14.02 ×(memristor-based PIM) and 10.48 ×(CMOS-based PIM), on average.

关键词： Hardware Computer architecture Parallel processing Three-dimensional displays Computational modeling Graphics processing units Memristors

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Predicting Friendship Using a Unified Probability Model 7th

Predicting Friendship Using a Unified Probability Model

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7th CCF Academic Conference on BigData, CCF BigData 2019

作者： Kou, Zhijuan Wang, Hua Yuan, Pingpeng Jin, Hai Xie, Xia National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9789811518980

Now, it is popular for people to share their feelings, activities tagged with geography and temporal information in Online Social Networks (OSNs). The spatial and temporal interactions occurred in OSNs contain a wealth of information to indicate friendship between persons. Existing researches generally focused on single dimension: spatial or temporal dimension. The simplified model only works in limited scenarios. Here, we aim to understand the probability of friendship and the place and time of interactions. First, spatial similarity of interactions is defined as a vector of places where persons checked in. Second, we employ exponential functions to characterize the change of strength of interactions as time goes on. Finally, a unified probability model to predict friendship between two persons is given. The model contains two sub-models based on spatial similarity and temporal similarity respectively. The experimental results on four data sets including spatial data sets (Gowalla and Weeplaces) and temporal data sets (Higgs Twitter Data set, High school Call Data set) show that our model works as expected. © Springer Nature Singapore Pte Ltd 2019.

关键词： Social networking (online)

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Superpage-Friendly Page Table Design for Hybrid Memory Systems

Superpage-Friendly Page Table Design for Hybrid Memory Syste...

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2020国际计算机前沿大会

作者： Xiaoyuan Wang Haikun Liu Xiaofei Liao Hai Jin National Engineering Research Center for Big Data Technology and System Huazhong University of Science and Technology Service Computing Technology and System Lab Huazhong University of Science and Technology Cluster and Grid Computing Lab Huazhong University of Science and Technology School of Computer Science and Technology Huazhong University of Science and Technology

Page migration has long been adopted in hybrid memory systems comprising dynamic random access memory(DRAM) and non-volatile memories(NVMs), to improve the system performance and energy ***, page migration introduces some side effects, such as more translation lookaside buffer(TLB) misses, breaking memory contiguity, and extra memory accesses due to page table updating. In this paper, we propose superpagefriendly page table called SuperPT to reduce the performance overhead of serving TLB misses. By leveraging a virtual hashed page table and a hybrid DRAM allocator, SuperPT performs address translations in a flexible and efficient way while still remaining the contiguity within the migrated pages.

关键词： Pagetable Hybridmemorysystem Pagemigration Multiplepagesizes Addresstranslation

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Towards dataflow based graph processing

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Science China(Information Sciences) 2017年第12期60卷 274-276页

作者： Hai JIN Pengcheng YAO Xiaofei LIAO Service Computing Technology and System Lab Cluster and Grid Computing Lab Big Data Technology and System Lab School of Computer Science and Technology Huazhong University of Science and Technology

Modern graph processing is widely used for solving a vast variety of real-world problems,e.g.,web sites ranking[1]and community detection[2].To better adapt and express the procedure of graph iteration,a wide spectrum... 详细信息

关键词： ILP cycle Towards dataflow based graph processing

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Echo: An Edge-Centric Code Offloading System with Quality of service Guarantee

arXiv

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arXiv 2018年

作者： Lin, Li Liao, Xiaofei Service Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

Code offloading is promising to accelerate mobile applications and save energy of mobile devices by shifting some computation to cloud. However, existing code offloading systems suffer from a long communication delay between mobile devices and cloud. To address this challenge, in this paper, we consider to deploy edge nodes in the proximity of mobile devices, and study how they benefit code offloading. We design an edge-centric code offloading system, called Echo, over a three-layer computing hierarchy consisting of mobile devices, edge and cloud. A critical problem needs to be addressed by Echo is to decide which method should be offloaded to which computing platform (edge or cloud). Different from existing offloading systems that let mobile devices individually make offloading decisions, Echo implements a centralized decision engine at the edge node. This edge-centric design can fully exploit the limited hardware resources at the edge to provide an offloading service with Quality of service guarantee. Furthermore, we propose some novel mechanisms, e.g., lazy object transmission and differential object update, to further improve system performance. The results of a small-scale real deployment and trace-driven simulations show that Echo significantly outperforms existing code offloading systems at both execution time and energy consumption. Copyright © 2018, The Authors. All rights reserved.

关键词： Edge computing

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LaLDPC: Latency-aware LDPC for read performance improvement of solid state drives 33

LaLDPC: Latency-aware LDPC for read performance improvement ...

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33rd International Conference on Massive Storage Systems and technology, MSST 2017

作者： Du, Yajuan Zou, Deqing Li, Qiao Shi, Liang Jin, Hai Xuey, Chun Jason Service Computing Technology and System Lab Cluster and Grid Computing Lab Big Data Technol. and Syst. Lab Sch. of Comp. Sci. and Technology Huazhong Univ. of Sci. and Technol. Wuhan430074 China Department of Computer Science City University of Hong Kong Kowloon Hong Kong College of Computer Science Chongqing University Chongqing China

High-density Solid State Drives (SSDs) have to use Low-Density Parity-Check (LDPC) codes to store data reliably. Current LDPC implementations apply multiple read-retry steps to find the appropriate set of multiple Reference Voltage (RVs) for successful decoding. These appropriate RVs, number of which is represented by read level, cannot be obtained in advance, instead, an iterative read-retry LDPC process happens that starts with the first read level with the smallest number of RVs and then increases the level until that the data have been successfully decoded. Only read-retry with the last read level, called the appropriate read level, is necessary. Read latency can be improved by avoiding read-retries. This becomes particularly important in the late stage of SSD life when high read levels are needed. To avoid unnecessary read-retries, this paper proposes Latency-aware LDPC (LaLDPC). We study read level characteristics along with data retention and observe that a single read level stays appropriate for a long time. During this time, all reads in the same page have probably the same appropriate read level, which we call the temporal read level locality. Using this value, LaLDPC estimates the starting read voltage level, which we store in the flash translation layer of the controller. As an example, we show how to integrate LaLDPC into the Demand-based Flash Translation Layer (DFTL). A new cache eviction algorithm is also proposed to leave entries with high read levels in the cache as long as possible. Experimental results show that LaLDPC saves 56% of read retries and improves SSD read performance by 18% on average compared with the existing LDPC method. © 33rd International Conference on Massive Storage Systems and technology, MSST 2017. All rights reserved.

关键词： Forward error correction

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