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Multi-Conference on software engineering, SE 2013

作者： Jung, Reiner Schneider, Christian Hasselbring, Wilhelm Software Engineering Research Group Kiel University Germany Embedded and Realtime Systems Research Group Kiel University Germany

ISBN: (纸本)9783885796091

Model-driven software development employs models to describe different aspects of a system on different levels of abstraction. These aspects are driven by technology or application domain. Modeling is often done in specific graphical or textual notations, called domain-specific languages (DSL). In recent years such languages became very popular in the modeling community to describe structure and sometimes behavior. In the context of type systems, these structures are called types and the behavior is modeled with expressions. The programming language community has developed many concepts to model and specify type systems and the semantics of expressions. However, in the modeling community this is often neglected when specifying meta models and describing their semantics, what may cause problems in developing checks and generators for DSLs. To address this issue, we present an approach, that provides guidance and support during DSL development based on established knowledge on type systems and generator construction, to ease the integration of type systems in DSL. We evaluate this approach with the Xtext language engineering framework. © Gesellschaft für Informatik, Bonn 2013.

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A HW/SW Co-verification framework for systemc

A HW/SW Co-verification framework for systemc

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作者： Herber, Paula Glesner, Sabine International Computer Science Institute 1947 Center Street Berkeley CA 94704 United States Software Engineering for Embedded Systems Group Technical University of Berlin Ernst-Reuter-Platz 7 10587 Berlin Germany

SystemC is widely used for modeling and simulation in hardware/software co-design. However, existing verification techniques are mostly ad-hoc and non-systematic. In this article, we present a systematic, comprehensive, and formally founded co-verification framework for digitalHW/SW systems that are modeled in SystemC. The framework is based on a formal semantics of SystemC and uses a combination of model checking and testing, whereby testing includes both the automated generation of timed inputs and automated conformance evaluation. We demonstrate its performance and its error detecting capability with two case studies, namely a packet switch and an anti-slip regulation and anti-lock braking system. © 2013 ACM.

关键词： Semantics

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VOICE OF EVIDENCE Organizational Culture and Success in SPI Initiatives

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IEEE software 2012年第3期29卷 97-99页

作者： Passos, Odette Mestrinho Dias-Neto, Arilo Claudio Barreto, Raimundo da Silva Institute of Exact Sciences and Technology Federal University of Amazonas Brazil Institute of Computing Experimentation and Testing on Software Engineering Group Federal University of Amazonas Brazil Institute of Computing complex embedded systems research group Federal University of Amazonas Brazil

To succeed, a software quality improvement (SQI) initiative must reflect organizational culture and the values that compose it. A study to define these values in software organizations includes proposals for implement... 详细信息

关键词： software Quality software Process Improvement

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Static analysis of run-time modes in synchronous process network

Static analysis of run-time modes in synchronous process net...

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8th International Ershov Informatics Conference on Perspectives of System Informatics, PSI 2011

作者： Beyer, Michael Glesner, Sabine Software Engineering for Embedded Systems Group Technische Universität Berlin Ernst-Reuter-Platz 7 Berlin 10587 Germany

ISBN: (纸本)9783642297083

For modeling modern streaming-oriented applications, Process Networks (PNs) are used to describe systems with changing behavior, which must be mapped on a concurrent architecture to meet the performance and energy constraints of embedded devices. Finding an optimal mapping of Process Networks to the constrained architecture presumes that the behavior of the Process Network is statically known. In this paper we present a static analysis for synchronous PNs that extracts different run-time modes by using polyhedral abstraction. The result is a Mealy machine whose states describe different run-time modes and the edges among them represent transitions. This machine can be used to guide optimizing backend mappings from PNs to concurrent architectures. © 2012 Springer-Verlag Berlin Heidelberg.

关键词： Static analysis

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Self-Stabilizing Micro Controller for Large-Scale Sensor Networks in Spite of Program Counter Corruptions Due to Soft Errors

Self-Stabilizing Micro Controller for Large-Scale Sensor Net...

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International Conference on Parallel and Distributed systems (ICPADS)

作者： Christopher Boelmann Torben Weis Michael Engel Arno Wacker Distributed Systems Group University of Duisburg-Essen Duisburg Germany Design Automation for Embedded Systems Group TU Dortmund University Dortmund Germany Software-engineering for Ubiquitous-Computing Applications University of Kassel Kassel Germany

For large installations of networked embedded systems it is important that each entity is self-stabilizing, because usually there is nobody to restart nodes that have hung up. Self-stabilization means to recover from temporary failures (soft errors) and adapt to a change of network topology caused by permanent failures. On the software side self-stabilizing algorithms must assume that the hardware is executing the software correctly. In this paper we discuss cases in which soft errors invalidate this assumption, especially in cases where CPU registers or the watchdog timer are affected by the fault. Based on the observation that a guaranteed self-stabilization is only possible as long as the watchdog-timer is working properly after temporary failures, we propose and compare three different approaches that meet the requirements of sensor networks, to solve this problem with a combination of hardware- and software-modifications: 1) A run-time verification of every watchdog access 2) A completely hardware-based approach, without any software modifications 3) A 2 X byte code alignment, to realign a corrupted program counter Furthermore we determine the average code-size increase and evaluate necessary hardware-modifications that come along with each approach.

关键词： Registers Hardware Random access memory Read only memory Microprocessors embedded systems

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Scalable multi-core simulation using parallel dynamic binary translation

Scalable multi-core simulation using parallel dynamic binary...

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2011 11th International Conference on embedded Computer systems: Architectures, Modeling and Simulation, IC-SAMOS 2011

作者： Almer, Oscar Böhm, Igor Von Koch, Tobias Edler Franke, Björn Kyle, Stephen Seeker, Volker Thompson, Christopher Topham, Nigel Institute for Computing Systems Architecture University of Edinburgh United Kingdom Software Engineering for Embedded Systems Group Technical University Berlin Germany

ISBN: (纸本)9781457708008

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc MultiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core 86 host machine for as many as 2048 target processors whilst exhibiting minimal and near constant overhead. © 2011 IEEE.

关键词： embedded systems

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Test-Case Generation for embedded Binary Code Using Abstract Interpretation 6

Test-Case Generation for Embedded Binary Code Using Abstract...

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6th Doctoral Workshop on Mathematical and engineering Methods in Computer Science, MEMICS 2010

作者： Reinbacher, Thomas Brauer, Jörg Horauer, Martin Steininger, Andreas Kowalewski, Stefan Embedded Computing Systems Group Institute of Computer Engineering Vienna University of Technology Treitlstrasse 3 ViennaA-1040 Austria Embedded Software Laboratory RWTH Aachen University Ahornstraße 55 AachenD-52074 Germany Department of Embedded Systems University of Applied Sciences Technikum Wien Höchstädtplatz 5 ViennaA-1200 Austria

ISBN: (纸本)9783939897224

This paper describes a framework for test-case generation for microcontroller binary programs using abstract interpretation techniques. The key idea of our approach is to derive program invariants a priori, and then use backward analysis to obtain test vectors that are executed on the target microcontroller. Due to the structure of binary code, the abstract interpretation framework is based on propositional encodings of the program semantics and SAT solving. © Thomas Reinbacher, Jörg Brauer, Martin Horauer, Andreas Steininger, and Stefan Kowalewski;licensed under Creative Commons License NC-ND

关键词： Binary codes

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Verification of Distributed embedded Real-Time systems and their Low-Level Implementations Using Timed CSP

Verification of Distributed Embedded Real-Time Systems and t...

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Asia-Pacific Conference on software engineering

作者： Bjorn Bartels Sabine Glesner Software Engineering Group Berlin Institute of Technology Berlin Germany Software Engineering for Embedded Systems Group Berlin Institute of Technology Berlin Germany

Process algebras like Timed CSP offer a convenient level of abstraction for the specification and verification of distributed embedded real-time systems. Complex systems can be specified in terms of interacting modules whose interaction can be analyzed using the mechanisms of the process algebra. In this paper, we present a development approach that supports the construction of distributed real-time systems by exploiting Timed CSP's concept of modularity. Individual system components are refined to their low-level implementations and shown to be a formally correct implementation of their respective Timed CSP specifications. Their interaction can then be analyzed by composing the individual process specifications. The key idea underlying the presented approach is a formal relation between timed process algebraic specifications and implementations given in a general purpose programming language.

关键词： Semantics Algebra Timing Hardware Registers Load modeling Data models

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Scalable multi-core simulation using parallel dynamic binary translation

Scalable multi-core simulation using parallel dynamic binary...

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International Conference on embedded Computer systems: Architectures, Modeling and Simulation (IC-SAMOS)

作者： Oscar Almer Igor Böhm Tobias Edler von Koch Björn Franke Stephen Kyle Volker Seeker Christopher Thompson Nigel Topham Institute of Computing Systems Architecture University of Edinburgh UK Software Engineering for Embedded Systems Group Technical University of Berlin Germany

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (ISS) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (JIT) dynamic binary translation (DBT). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (ISA). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and EEMBC MULTIBENCH benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core ×86 host machine for as many as 2048 target processors whilst exhibiting minimal and near constant overhead.

关键词： Program processors Multicore processing Random access memory Hardware Computational modeling Field programmable gate arrays Benchmark testing

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Safe automotive software

Safe automotive software

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Lecture Notes in Computer Science

作者： Heckemann, Karl Gesell, Manuel Pfister, Thomas Berns, Karsten Schneider, Klaus Trapp, Mario Fraunhofer Institute for Experimental Software Engineering Fraunhofer-Platz 1 67663 Kaiserslautern Germany Embedded Systems Group Department of Computer Science University of Kaiserslautern Germany Robotics Research Lab. Department of Computer Science University of Kaiserslautern Germany

ISBN: (纸本)9783642238659

For automotive manufacturers and tier-1 suppliers, the upcoming safety standard ISO 26262 results in new requirements for the development of embedded electronics and software. In particular, the variety of driver assistance systems that autonomously influence the driving dynamics of a vehicle may have a high risk potential and require development in accordance with the normative guidelines. But especially for those systems whose function is typically not based solely on hardware but on complex software algorithms, safety certification can be very complex or even impossible. In this paper the problems of development of vehicle systems according to ISO 26262 are described. Finally an approach for a safety-oriented reference architecture is presented that introduces adaptive software safety cages. This architecture enables application of formal verification methods. Supported by multisensor data fusion this allows to reduce safety requirements for vehicle control systems. © 2011 Springer-Verlag.

关键词： Control system synthesis

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