Consideration of an embedded system's timing behaviour and power consumption at system-level is increasingly important nowadays but it is also an ambitious task. Sophisticated tools and techniques exist for power ...
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Due to the continuous shrinking of the transistor sizes which is strongly driven by Moore's law, reliability becomes a dominant design challenge for embedded systems. Reliability problems arise from permanent erro...
详细信息
Due to the continuous shrinking of the transistor sizes which is strongly driven by Moore's law, reliability becomes a dominant design challenge for embedded systems. Reliability problems arise from permanent erro...
详细信息
Due to the continuous shrinking of the transistor sizes which is strongly driven by Moore's law, reliability becomes a dominant design challenge for embedded systems. Reliability problems arise from permanent errors due to manufacturing, process variations, aging as well as soft errors. As a result, the hardware will consist of unreliable components and hence, the development of embedded systems has to change fundamentally. Therefore, we propose a dependability-aware design approach for hardware systems through integrating dependability into a state-of-the-art system-level design language. Our approach is based on SystemC and extends the Program State Machine model to explicitly observe, diagnose, and compensate faulty behavior. Different compensation mechanisms like run-time reconfiguration or mechanisms for error propagation can be used by the designer during refinement. They are controlled by a new exception-like mechanism. Furthermore, our approach aims to integrate functional verification as well as dependability verification with respect to given fault models.
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