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检索条件"机构=Heinz Nixdorf Institute System and Circuit Technology"

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Dynamically reconfigurable system-on-programmable-chip

Dynamically reconfigurable system-on-programmable-chip

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Euromicro Conference on Parallel, Distributed and Network-Based Processing

作者： H. Kalte D. Langen E. Vonnahme A. Brinkmann U. Ruckert Heinz Nixdorf Institute System and Circuit Technology University of Paderborn Paderborn Germany

ISBN: (纸本)0769514448

Today's high-density FPGAs and intellectual property (IP) components enable the integration of complex systems in one programmable chip. New design strategies and concepts have to be developed in order to utilize the new system-level integration facilities. The approach introduced in this paper describes the implementation of a communication infrastructure that provides a number of on-chip IP-sockets. By using the FPGA feature of partial dynamic reconfiguration, different IP components can be plugged into these sockets at run-time. This leads to a reconfigurable system that can be adapted to varying demands. In this context, we designed a 32-bit RISC processor and an AMBA (Advanced Microcontroller Bus Architecture) on-chip interconnection bus. Finally, we mapped these components on to a reconfigurable system-level FPGA. The resulting hardware sizes and the utilization of the FPGA's resources are presented.

关键词： Field programmable gate arrays Programmable logic devices Programmable logic arrays Runtime Logic devices Clocks Digital signal processing Design engineering Cost function Identity-based encryption

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A distributed simulator for large networks used in building automation systems

A distributed simulator for large networks used in building ...

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IEEE International Workshop on Factory Communication systems (WFCS)

作者： R. Hunstock S. Ruping U. Ruckert Heinz Nixdorf Institute System and Circuit Technology University of Paderborn Paderborn Germany

In modern building automation systems an increasing number of devices with computational facilities exchange data and interoperate using underlying control networks. Discontinuous and nonlinear processes, synchronization effects and delays in communication lead to systems with highly complex behavior. Analytical methods often do not meet the demands for the evaluation of such systems. As an alternative approach, discrete event simulation gains more and more importance. The authors present the development of a distributed software simulator especially designed for large automation systems consisting of thousands of microcontroller based devices. An existing and expanding building automation system used to validate the simulator and which forms a base for modeling a large system is also described.

关键词： Computational modeling Computer networks Automatic control Communication system control Control systems Delay effects Discrete event simulation Software design Design automation Microcontrollers

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Measurements in switched Ethernet networks used for automation systems

Measurements in switched Ethernet networks used for automati...

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IEEE International Workshop on Factory Communication systems (WFCS)

作者： E. Vonnahme S. Ruping U. Ruckert Heinz Nixdorf Institute System and Circuit Technology University of Paderborn Paderborn Germany

Ethernet networks for automation systems promise standardized interworking between completely different devices from field level up to office level without connection and conversion difficulties. As Ethernet was not originally developed considering automation system requirements, its qualification, especially regarding topology and determinism demands, has to be examined. Theoretical calculations on topology influence are completed by measurements on switch hardware. A special software for configuring, monitoring and testing the switch hardware was developed. Further experiments for the evaluation of the Ethernet Medium Access Control Pause operation in automation systems are also described.

关键词： Intelligent networks Ethernet networks Switches Network topology Protocols Manufacturing automation Equations circuits Monitoring Software testing

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High level estimation of the area and power consumption of on-chip interconnects

High level estimation of the area and power consumption of o...

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Annual IEEE International ASIC/SOC Conference

作者： D. Langen A. Brinkmann U. Ruckert Heinz Nixdorf Institute System and Circuit Technology University of Paderborn Paderborn Germany

This paper addresses the problem of estimating the power and area consumption of on-chip interconnects for standard cell ASIC processes. We introduce a set of analytic investigations on buses, crossbar switches, and multiplexors. Furthermore, we prove the accuracy of the results by comparing them with gate-level power-estimations on a double metal 0.6 /spl mu/m CMOS technology.

关键词： Energy consumption Integrated circuit interconnections Power system interconnection system-on-a-chip Switches CMOS technology Libraries Decoding Protocols LAN interconnection

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A bootstrapping method for autonomous and in site learning of generic navigation behaviour

A bootstrapping method for autonomous and in site learning o...

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International Conference on Pattern Recognition

作者： B. Iske U. Ruckert K. Malmstrom J. Sitte Heinz Nixdorf Institut System and Circuit Technology University of Paderborn Paderborn Germany School of Manufactural Engineering Queensland University of Technology Brisbane Australia School of Computing Science Queensland University of Technology Brisbane Australia

ISBN: (纸本)0769507506

To understand the behaviour of natural autonomous systems, research is carried out on artificial autonomous agents. The paper focuses on how simple behaviours can be learnt autonomously using a bootstrapping method. Firstly, a two dimensional self-organising map is realised which provides the agent's sense of orientation. Once this relative positioning system has been established, the agent learns to navigate towards a target using the reinforcement learning technique of Q-learning. Since only neural network processing is used, this technique emulates the distributed and adaptive information processing found in natural autonomous systems. Furthermore, due to its generality, the neural implementation developed is transferable to other artificial autonomous agents with different sensors and effector suites.

关键词： Navigation Autonomous agents Robot sensing systems Infrared sensors Artificial neural networks Information processing Robotics and automation Frequency Sensor phenomena and characterization circuits

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DiSiA - A digital chip design for smart antennas

DiSiA - A digital chip design for smart antennas

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IEEE VTS 50th Vehicular technology Conference, VTC 1999-Fall

作者： Kuipers, Martin Wiegmann, Mark Rüping, Stefan Department of Communications Engineering University of Paderborn Germany Heinz Nixdorf Institute System and Circuit Technology University of Paderborn Germany

ISBN: (纸本)0780354354

Smart array antennas are well suited for optimising the signal to noise ratio in mobile communications. While the performance of smart array antennas rise by using more antenna elements, the digital signal processing of the element signals becomes more expensive for large antennas. Therefore, the digital signal processor DiSiA (Digital Signal processor for intelligent Antennas) was developed. Besides mixing and beamforming, the DiSiA does a distributed addition of the base band signals, in case of receiving. An intelligent multiplex control enables the use of SDMA without needing all element signals in a central processing unit. In case of transmitting, each DiSiA performs beamforming employing multiple independent signals. Simulation results show the overall performance of the signal path. © 1999 IEEE.

关键词： Digital signal processors

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Mixed mode VLSI implementation of a neural associative memory

Mixed mode VLSI implementation of a neural associative memor...

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Proceedings of the International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired systems, MicroNeuro

作者： A. Heittmann U. Ruckert System and Circuit Technology Heinz Nixdorf Institute University of Paderborn Paderborn Germany Universitat Paderborn Paderborn Nordrhein-Westfalen DE

A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a n/spl times/m matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. Although analog circuits suffer from device mismatch a moderate precision of the circuit is acceptable since for the given associative memory model only few parts of the circuit participate on the performed information processing steps. Thus, the information processing elements can be integrated very densely on one chip and hence large scale integration with a large number of connection weights is feasible.

关键词： Very large scale integration Associative memory Analog circuits Hardware Information processing Large scale integration Electronic mail Memory architecture Neural networks circuit testing

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Artificial neural networks for autonomous robot control: reflective navigation and adaptive sensor calibration

Artificial neural networks for autonomous robot control: ref...

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International Conference on Neural Information Processing

作者： A. Loffler J. Klahold U. Ruckert Heinz Nixdorf Institute System and Circuit Technology University of Paderborn Paderborn Germany Universitat Paderborn Paderborn Nordrhein-Westfalen DE

The authors present the application of artificial neural networks to the control of a mobile autonomous robot, which is acting in a totally unknown and-most importantly-dynamically changing environment. In particular, the employment of interacting 'simple', i.e. hand-designed, neural networks for navigation purposes is investigated as well as a variation of self-organizing maps for adaptive sensor calibration. We take a pragmatic point of view as the minimal condition imposed on the developed algorithms: that they do well on a real system acting in a real environment. Hence, the design of all of the implemented neural networks is clearly motivated by their applicability. In this context, special considerations are dedicated to ensure robustness, real-time capability and memory resourcefulness. In order to practically demonstrate the obtained results, the mini-robot Khepera is utilized as an experimentational platform, which is (due to its small size), a versatile tool for scientific investigation.

关键词： Artificial neural networks Robot control Mobile robots Robot sensing systems Employment Navigation Self organizing feature maps Calibration Neural networks Robustness

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Analysis of IC fabrication processes using self-organizing maps

Analysis of IC fabrication processes using self-organizing m...

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1999 Ninth International Conference on Artificial Neural Networks ICANN 99. (Conf. Publ. No. 470)

作者： S. Ruping J. Muller Heinz Nixdorf Institut System and Circuit Technology University of Paderborn Paderborn Germany Automotive Equipment Division 8 Robert Bosch GmbH Reutlingen Germany

The analysis of integrated circuit (IC) fabrication processes is an important task in order to optimize the yield and to detect problems in very early state. Neural networks seem to be a promising approach to data analysis, especially when there is a large amount of data with many nonlinearities. In this paper we describe the use of self-organizing maps (SOM) for visualization and analysis of data derived from a running IC production of the Robert Bosch GmbH Waferfab at Reutlingen, Germany. The main aspects are techniques for pressure sensor trimming and online process monitoring for in-process data, parameters and the process status. After a short description of visualization techniques for SOM, we present the results based on the real world data from the Waferfab.

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HiBRIC-MEM, a memory controller for PowerPC based systems

HiBRIC-MEM, a memory controller for PowerPC based systems

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23rd Euromicro Conference on New Frontiers of Information technology

作者： Porrmann, M Landmann, J Marks, KM Ruckert, U Heinz Nixdorf Institute University of Paderborn System and Circuit Technology 33 102 Paderborn Fuerstenallee 11 Germany

ISBN: (纸本)0818681306

This paper describes the architecture and development of an innovative memory controller for the PowerPC family. HiBRIC-MEM (High Bandwidth Resource Interface Controller) provides control for up to two PowerPC processors. A look-ahead mechanism, called stream cache, is used to reduce the effective memory latency and a 12-bit error correction code is available for optimal system security. Initial silicon was produced in a 0.7 mu m, three metal layer Motorola technology and has a die size of 12.1 x 12.1 mm(2). HiBRIC-MEM is used e.g. in a commercially available parallel computer.

关键词： Data storage equipment

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