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A SELF-CONSISTENT MODEL OF GAMMA-X MIXING IN GAAS/ALAS/GAAS QUANTUM-WELL STRUCTURES USING THE QUANTUM TRANSMITTING BOUNDARY METHOD

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JOURNAL OF APPLIED PHYSICS 1993年第8期74卷 5053-5060页

作者： SUN, JP MAINS, RK YANG, K HADDAD, GI Center for High‐Frequency Microelectronics Solid State Electronics Laboratory Department of Electrical Engineering and Computer Science The University of Michigan Ann Arbor Michigan 48109

We present a numerical study of the GAMMA-X mixing in GaAs/AlAs/GaAs quantum well structures. A GAMMA-X mixing model proposed by Liu [Appl. Phys. Lett. 51, 1019 (1987)] is extended to include the effects of self-consistency and nonzero transverse momentum. In the present model, the coupled Schrodinger equations for GAMMA and X electron envelope wave functions are solved self-consistently with Poisson's equation to calculate the electron transmission probability and wave functions, which lead to the current-voltage (I-V) characteristics of single barrier and double barrier resonant tunneling diode structures. The quantum transmitting boundary method is employed in the model for numerical solution of the coupled Schrodinger equations, which proves to be very stable and efficient, even for large (> 2000 angstrom) structures. The features of GAMMA-X mixing, such as the resonance/antiresonance in the transmission probability and the virtual bound states, are clearly demonstrated. Additional physical features are observed in the transmission probability and the wave functions under applied bias conditions. Our work shows that inclusion of transverse momentum, variable effective mass, and the self-consistent potential is important in the realistic modeling of I-V characteristics for structures exhibiting GAMMA-X coupling.

关键词： QUANTUM WELLS GALLIUM ARSENIDES ALUMINIUM ARSENIDES IV CHARACTERISTIC BAND STRUCTURE SCHROEDINGER EQUATION WAVE FUNCTIONS POISSON EQUATION TRANSMISSION SELF?CONSISTENT FIELD NUMERICAL SOLUTION

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Dynamic partitioning to mitigate stuck-at faults in emerging memories 36

Dynamic partitioning to mitigate stuck-at faults in emerging...

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36th IEEE/ACM International Conference on computer-Aided Design, ICCAD 2017

作者： Zhang, Jiangwei Kline, Donald Fang, Liang Melhem, Rami Jones, Alex K. State Key Laboratory of High Performance Computing College of Computer National University of Defense Technology China Department of Electrical and Computer Engineering University of Pittsburgh United States Department of Computer Science University of Pittsburgh United States

ISBN: (纸本)9781538630938

Emerging non-volatile memories have many advantages over conventional memory. Unfortunately, many are susceptible to write endurance challenges, resulting in stuck-at faults. Existing mitigation methods statically partition and invert data within a block containing such faults (partition-and-flip) to ensure data is written to match stuck-at cells such that they may remain in service. Unfortunately, these schemes have limited fault tolerance capabilities and require the assumption that their auxiliary bits are fault free. We propose a dynamic partitioning scheme that improves the number of tolerated stuck-at faults and simultaneously protects auxiliary bits. Dynamic partitioning can significantly improve the fault tolerance over existing static partitioning approaches with an equal number of auxiliary bits. Moreover, it can often still improve fault tolerance while reducing the number of auxiliary bits. Compared to flip-N-write and Aegis, a leading mitigation scheme, dynamic partitioning can achieve 7-72% and 5-53 x lower write error rates, respectively, for the same capacity overhead with a stuck-at-fault rate of 10-3. © 2017 IEEE.

关键词： Fault tolerance

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Yoda: Judge me by my size, do you? 35

Yoda: Judge me by my size, do you?

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35th IEEE International Conference on computer Design, ICCD 2017

ISBN: (纸本)9781538622544

Phase change memory is a promising alternative to conventional memories such as DRAM due to its density and non-volatility. Unfortunately, reliability is still a challenge as limited write endurance, exacerbated by process variation, leads to increasing numbers of stuck-at faults over the memory's lifetime. Error-correcting Pointers (ECP) is a popular proposal to mitigate stuck-at faults by recording the addresses and the values of faulty bits in order to extend the memory lifetime. In this paper, we propose Yoda, a method to extend ECP with one or a small number of additional encoding bits in order to dramatically improve the effectiveness and guaranteed fault correction capability of ECP. Our simulation results demonstrate that Yoda has a 3.0x improvement in fault coverage compared to a fault-aware ECP with a similar overhead, while also providing a 2.5-3.0x improvement over state-of-the-art schemes with comparable complexity. © 2017 IEEE.

关键词： Phase change memory

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high-confidence software evolution

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science China(Information sciences) 2016年第7期59卷 94-112页

作者： Qing GAO Jun LI Yingfei XIONG Dan HAO Xusheng XIAO Kunal TANEJA Lu ZHANG Tao XIE Key Laboratory of High Confidence Software Technologies Mo E Institute of Software School of Electronics Engineering and Computer Science Peking University NEC Laboratories America Inc. 3. Accenture Technology Labs 4. Department of Computer Science University of Illinois at Urbana-Champaign

Software continues to evolve due to changing requirements, platforms and other environmental pressures. Modern software is dependent on frameworks, and if the frameworks evolve, the software has to evolve as well. On the other hand, the software may be changed due to changing requirements. Therefore, in high-confidence software evolution, we must consider both framework evolution and client evolution, each of which may incur faults and reduce software quality. In this article, we present a set of approaches to address some problems in high-confidence software evolution. In particular, to support framework evolution, we propose a history-based matching approach to identify a set of transformation rules between different APIs, and a transformation language to support automatic transformation. To support client evolution for high-confidence software, we propose a path-exploration-based approach to generate tests efficiently by pruning paths irrelevant to changes between versions, several coverage-based approaches to optimize test execution, and approaches to locate faults and fix memory leaks automatically. These approaches facilitate high-confidence software evolution from various aspects.

关键词： software evolution high confidence software quality software development program analysis

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MECHANISMS DETERMINING 3RD ORDER INTERMODULATION DISTORTION IN ALGAAS/GAAS HETEROJUNCTION BIPOLAR-TRANSISTORS

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 1992年第12期40卷 2374-2380页

作者： SAMELIS, A PAVLIDIS, D Center of High Frequency Microelectronics Solid State Electronics Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The third order intermodulation distortion (IMD3) mechanisms of HBT's are analyzed using Volterra Series theory. A T-equivalent circuit is used for the large-signal model of the HBT. The third order nonlinear currents generated by the device nonlinearities are evaluated for this purpose and current cancellation is discussed. It is found that, even though the C(je) and g(je) related currents do not show pronounced cancellation, the total base-emitter current and the total base-collector current cancel partially. Second harmonic loading is addressed in view of IMD3 optimization while, at the same time, maintaining high gain through conjugate matching at the fundamental frequency. IMD3 is very sensitive to the nonlinear currents generated by g(je) and alpha. Optimum IMD3 occurs at high second harmonic reflection coefficients corresponding to open load conditions. Finally, minimum and maximum IMD3 occurs for second harmonic load reflection coefficient phases close to analogous extremes of the dominant nonlinear current of the device.

关键词： Intermodulation distortion Gallium arsenide Heterojunction bipolar transistors Reflection Harmonic distortion Equivalent circuits Senior members Frequency dependence Dynamic range Microelectronics

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Adapting Memory Hierarchies for Emerging Datacenter Interconnects

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Journal of computer science & Technology 2015年第1期30卷 97-109页

作者：江涛侯锐董建波柴琳 Sally A. McKee 田斌张立新孙凝晖 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China Computer Science and Engineering Chalmers University of Technology Gothenburg 41296 Sweden National High Performance Integrated Circuit Design Center (Shanghai) Shanghai 201204 China

Efficient resource utilization requires that emerging datacenter interconnects support both high performance communication and efficient remote resource sharing. These goals require that the network be more tightly coupled with the CPU chips. Designing a new interconnection technology thus requires considering not only the interconnection itself, but also the design of the processors that will rely on it. In this paper, we study memory hierarchy implications for the design of high-speed datacenter interconnects particularly as they affect remote memory access -- and we use PCIe as the vehicle for our investigations. To that end, we build three complementary platforms： a PCIe-interconnected prototype server with which we measure and analyze current bottlenecks; a software simulator that lets us model microarchitectural and cache hierarchy changes; and an FPGA prototype system with a streamlined switchless customized protocol Thunder with which we study hardware optimizations outside the processor. We highlight several architectural modifications to better support remote memory access and communication, and quantify their impact and ]imitations.

关键词： high-speed interconnect memory hierarchy time shared memory datacenter network

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DESIGN AND EXPERIMENTAL CHARACTERISTICS OF STRAINED IN0.52AL0.48AS/INXGA1-XAS (X-GREATER-THAN-0.53) HEMTS

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IEEE TRANSACTIONS ON ELECTRON DEVICES 1989年第10期36卷 2249-2259页

作者： NG, GI PAVLIDIS, D JAFFE, M SINGH, J CHAU, HF Center for High Frequency Microelectronics Solid State Electronics Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA IBM VT USA

Strained In/sub 0.52/Al/sub 0.48/ As/In/sub x/Ga/sub 1-x/As (x>0.53) HEMTs (high electron mobility transistors) are studied theoretically and experimentally. A device design procedure is reported that is based on band structure and charge control self-consistent calculations. It predicts the sheet carrier density and electron confinement as a function of doping and thickness of layers. The DC performance at 300 K is presented. Wafer statistics demonstrate improvement of device characteristics with excess indium in the channel (g/sub m,/ /sub intr/=500 and 700 mS/mm for x=0.60 and 0.65). Microwave characterization shows the f/sub T/ improvement (f/sub T/=40 and 45 GHz for x=0.60 and 0.65, respectively) and the R/sub ds/ limitations of the 1- mu m-long-gate HEMTs.< >

关键词： Indium gallium arsenide Charge carrier density Electron mobility Indium compounds Carrier confinement Gallium arsenide Cutoff frequency Effective mass Microelectronics Solid state circuits

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A channel-level RAID5 schema based physical address in SSD 20th

A channel-level RAID5 schema based physical address in SSD

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20th Annual Conference on computer engineering and Technology, NCCET 2016

作者： Feng, Ya Xing, Yuxuan Xiao, Nong Liu, Fang State Key Laboratory of High Performance Computing Department of Computer Science National University of Defense Technology Changsha China

ISBN: (纸本)9789811031588

Flash-based solid state disks (SSDs) have been widely used for its high performance, low power, and concurrency features. With the increase in storage capacity, the reliability problem of SSD is becoming increasingly serious. In this paper, we implemented a technique based SSDs by constructing RAID-5 to enhance the reliability of SSD while maintaining its performance. First, we construct RAID-5 stripe based on SSD physical address which means no mapping tables to store stripe information. Second, our schema constructs dynamic stripe with log-structure to solve the inherent small write problem associated with conventional RAID-5. Third, since the correlation between data stripe, we realize garbage collection based on stripe group. Finally, we conduct extensive simulations using real-world traces and synthetic benchmarks in the SSDsim [1]. The experimental results show that we consume less than 7% of the performance and 6% of the storage consumption of SSD to achieve inner-channel RAID-5 to improve the reliability of SSD. © Springer Nature Singapore Pte Ltd. 2016.

关键词： Reliability

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Tunneling devices and applications in high functionality/speed digital circuits

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SOLID-STATE ELECTRONICS 1997年第10期41卷 1515-1524页

作者： Haddad, GI Mazumder, P Center for High Frequency Microelectronics Solid State Electronics Laboratory Electrical Engineering and Computer Science Department University of Michigan Ann Arbor MI 48 U.S.A.

Tunneling phenomena can be used to realize devices with unique IT-V characteristics (negative differential resistance) which can be employed to design various types of digital circuits with a significantly lower number of transistors, extremely fast switching speeds, very low power consumption and pipelining capability at the basic gate level (nanopipelining) which results in higher system throughput. In this article, we will present the basic properties of various types of devices which have been proposed for these applications including resonant tunneling diodes (RTDs), Esaki tunnel diodes (ETDs), and various types of transistors including resonant hot electron transistors (RHETs) and tuaneling bipolar transistors (TBTs). We will also compare the anticipated performance of various types of logic gates and digital circuit implementations utilizing these devices with conventional CMOS circuits. (C) 1997 Elsevier science Ltd.

关键词： Digital circuits

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Single-vehicle scheduling problem on a straight line with time window constraints 1st

Single-vehicle scheduling problem on a straight line with ti...

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1st Annual International Computing and Combinatorics Conference, COCOON 1995

作者： Chan, Chi-Lok Young, Gilbert H. High Performance Computing Laboratory Department of Computer Science The Chinese University of Hong Kong ShatinNT Hong Kong

ISBN: (纸本)354060216X

The problem of single-vehicle scheduling with ready time and deadline constraints can be apphcable to many practical transportation problems. But the general case is a generalization of classical Traveling Salesman Problem and it is NP-hard. Psaraftis et al. [5] presented an O(n 2) algorithm for vehicle scheduling problems where the topological structure of sites are restricted to straight hne and there is no deadline for each site. They conjectured that this problem is NP-hard if each site has an arbitrary ready time and deadline (called time window). In this paper, we prove the conjecture and show that the decision versions of vehicle scheduling problems on a straight hne topology with time window are NP-complete for both path and tour versions. We also give an O(n 2) algorithm to solve a special case of this problem in which all sites have a common ready time. This algorithm is applicable to both path and tour versions. Keywords: deadline, NP-complete, optimal schedule, ready time, vehicle scheduling problem, time windows. © 1995, Springer-Verlag. All Rights Reserved.

关键词： Traveling salesman problem

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