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Fault Tolerant Support Vector Machines

Fault Tolerant Support Vector Machines

引用

International Conference on Parallel Processing (ICPP)

作者： Sameh Shohdy Abhinav Vishnu Gagan Agrawal Department of Computer Science and Engineering The Ohio State University Columbus OH High Performance Computing Group Pacific Northwest National Laboratory Richland WA

ISBN: (纸本)9781509028245

Support Vector Machines (SVM) is a popular Machine Learning algorithm, which is used for building classifiers and models. Parallel implementations of SVM, which can run on large scale supercomputers, are becoming commonplace. However, these supercomputers -- designed under constraints of data movement -- frequently observe faults in compute devices. Many device faults manifest as permanent process/node failures. In this paper, we present several approaches for designing fault tolerant SVM algorithms. First, we present an in-depth analysis to identify the critical data structures, and build baseline algorithms that simply periodically checkpoint these data structures. Next, we propose a novel algorithm, which requires no inter-node data movement for checkpointing, and only O(n2/p2) recovery time -- a small fraction of the expected O(n3/p) time-complexity of SVM. We implement these algorithms and evaluate them on a large scale cluster. Our evaluation indicates that the overall data movement for checkpointing in the baseline algorithm can be up to 100x the dataset size!, while the proposed novel algorithm is completely communication-free of checkpointing. In addition, it saves up to 20x space, while providing better (by an average of 5.5x speedup on 256 cores) recovery time than the baseline algorithm with different number of checkpoints. The experiments also show that our communication avoiding algorithm outperforms Spark MLLib SVM implementation by an average of 6.4x with 256 cores in the case of failure.

关键词： Support vector machines Algorithm design and analysis Checkpointing Fault tolerance Fault tolerant systems Data structures Clustering algorithms

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Fault Tolerant Frequent Pattern Mining

Fault Tolerant Frequent Pattern Mining

引用

International Conference on high performance computing

ISBN: (纸本)9781509054121

FP-Growth algorithm is a Frequent Pattern Mining (FPM) algorithm that has been extensively used to study correlations and patterns in large scale datasets. While several researchers have designed distributed memory FP-Growth algorithms, it is pivotal to consider fault tolerant FP-Growth, which can address the increasing fault rates in large scale systems. In this work, we propose a novel parallel, algorithm-level fault-tolerant FP-Growth algorithm. We leverage algorithmic properties and MPI advanced features to guarantee an O(1) space complexity, achieved by using the dataset memory space itself for checkpointing. We also propose a recovery algorithm that can use in-memory and disk-based checkpointing, though in many cases the recovery can be completed without any disk access, and incurring no memory overhead for checkpointing. We evaluate our FT algorithm on a large scale InfiniBand cluster with several large datasets using up to 2K cores. Our evaluation demonstrates excellent efficiency for checkpointing and recovery in comparison to the disk-based approach. We have also observed 20x average speed-up in comparison to Spark, establishing that a well designed algorithm can easily outperform a solution based on a general fault-tolerant programming model.

关键词： Fault tolerance Fault tolerant systems Checkpointing Algorithm design and analysis Programming Sparks Data structures

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Accurate and efficient predicate analysis with binary decision diagrams

Accurate and efficient predicate analysis with binary decisi...

引用

IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： J.W. Sias W.W. Hwu D.I. August Center for Reliable and High-Performance Computing Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign IL USA Department of Computer Science Princeton University Princeton NJ USA

Functionality and performance of EPIC architectural features depend on extensive compiler support. Predication, one of these features, promises to reduce control flow overhead and to enhance optimization, provided that compilers can utilize it effectively. Previous work has established the need for accurate, direct predicate analysis and has demonstrated a few useful techniques, but has not provided an efficient, general framework. The paper presents the Predicate Analysis System (PAS), which maps knowledge of predicate and condition relations in general control flow onto a convenient logical substrate, the reduced ordered binary decision diagram. PAS is the first such framework to demonstrate direct, accurate, and efficient analysis of arbitrary condition and predicate define networks in arbitrary control flow.

关键词： Data structures Boolean functions Control systems performance analysis high performance computing computer science Fasteners Parallel processing Assembly Engines

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Blockchain and smart contract for digital certificate

Blockchain and smart contract for digital certificate

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International Conference on Applied System Innovation (ICASI)

作者： Jiin-Chiou Cheng Narn-Yih Lee Chien Chi Yi-Hua Chen Department of Computer Science and Information Engineering Southern Taiwan University of Science and Technology Tainan Taiwan National Applied Research Laboratories Natinal Center for High-Performance Computing

According to the Taiwan Ministry of Education statistics, about one million graduates each year, some of them will go to countries, high schools or tertiary institutions to continue to attend, and some will be ready to enter the workplace employment. During the course of study, the students' all kinds of excellent performance certificates, score transcripts, diplomas, etc., will become an important reference for admitting new schools or new works. As schools make various awards or diplomas, only the names of the schools and the students are input. Due to the lack of effective anti-forge mechanism, events that cause the graduation certificate to be forged often get noticed. In order to solve the problem of counterfeiting certificates, the digital certificate system based on blockchain technology would be proposed. By the unmodifiable property of blockchain, the digital certificate with anti-counterfeit and verifiability could be made. The procedure of issuing the digital certificate in this system is as follows. First, generate the electronic file of a paper certificate accompanying other related data into the database, meanwhile calculate the electronic file for its hash value. Finally, store the hash value into the block in the chain system. The system will create a related QR-code and inquiry string code to affix to the paper certificate. It will provide the demand unit to verify the authenticity of the paper certificate through mobile phone scanning or website inquiries. Through the unmodifiable properties of the blockchain, the system not only enhances the credibility of various paper-based certificates, but also electronically reduces the loss risks of various types of certificates.

关键词： Contracts Companies Conferences Technological innovation Distributed databases Certification

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Uniform Information Exchange in Multi-channel Wireless Ad Hoc Networks 17

Uniform Information Exchange in Multi-channel Wireless Ad Ho...

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International Conference on Autonomous Agents and Multiagent Systems

作者： Dongxiao Yu Li Ning Yong Zhang Hai Jin Yuexuan Wang Francis C. M. Lau Shengzhong Feng Services Computing Technology and System Lab Big Data Technology and System Lab Clusters and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Center for High Performance Computing Shenzhen Institutes of Advanced Technology CAS Department of Computer Science The University of Hong Kong

ISBN: (纸本)9781510855076

Information exchange is a basic primitive for maintaining the smooth running of a network or a system with multiple communicating agents. Given k packets initially stored at k nodes respectively, the problem is to disseminate the k packets to the whole network with the objective of minimizing the time used. We study this problem in single-hop multi-channel networks of n nodes, and target on devising uniform distributed protocols that do not rely on any prior knowledge of network parameters, such as the network size n or the number of packet holders k. Uniform protocols have better scalability and are more suitable for implementation in reality Specifically, we propose a uniform distributed protocol that with high probability accomplishes the dissemination in O(k/F+F·log n) rounds, assuming F available channels. This protocol is asymptotically optimal when k is large (k ≥ F~2 log n), and provides the best possible linear speedup with multiple channels comparing with the results using a single channel. To the best of our knowledge, this is the first uniform protocol for information exchange in multi-channel networks.

关键词： Information exchange Multi-channel networks Distributed algorithm Uniform protocol information exchange distributed algorithms MULTICHANNEL Packet Uniform Uniforms Mobile ad hoc networks distributed protocol network parameters single-channel

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Global and localized parallel preconditioning techniques for large scale solid Earth simulations

Global and localized parallel preconditioning techniques for...

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International Parallel and Distributed Processing Symposium, IPDPS 2003

作者： Wang, Kai Kim, Sangbae Zhang, Jun Nakajima, Kengo Okuda, Hiroshi Laboratory for High Performance Scientific Computing and Computer Simulation Department of Computer Science University of Kentucky LexingtonKY40506-0046 United States 2-2-54 Naka-Meguro Meguro-ku Tokyo153-0061 Japan Department of Quantum Engineering and System Sciences University of Tokyo 7-3-1 Hongo Bunkyo-ku Tokyo113-8656 Japan

ISBN: (纸本)0769519261

We investigate and compare a few parallel preconditioning techniques in the iterative solution of large sparse linear systems arising from solid Earth simulation with and without using contact information in the domain partitioning process. Previous studies are focused on using static or matrix pattern based incomplete LU (ILU) preconditioners in a localized preconditioner implementation. Our current studies are concerned with preconditioner performance for solving two different cases with and without known contact information. For the cases with contact information, we use localized threshold value based incomplete LU (ILUT) preconditioner to improve efficiency. For the cases without contact information, we use a global sparse approximate inverse preconditioner with a static sparsity pattern to achieve robustness. Numerical results from simulating ground motion on a parallel supercomputer are given to compare the effectiveness of these parallel preconditioning techniques. © 2003 IEEE.

关键词： Linear systems

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Complex Permeability Determination for EE Core Based on Flexible PCB Fixture and Magnetic Flux Path Length Analysis 2

Complex Permeability Determination for EE Core Based on Flex...

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2nd China Power Supply Society Electromagnetic Compatibility Conference, CPEMC 2024

作者： Jie, Huamin Zhao, Zhenyu Chang, Yongqi Wang, Changdong Jiang, Shiqi Gao, Richard Xian-Ke See, Kye Yak School of Electrical and Electronic Engineering Nanyang Technological University Singapore Singapore Department of Electrical and Computer Engineering National Univeristy of Singapore Singapore Singapore Department of Control Science and Engineering Harbin Institute of Technology Harbin China School of Electronics and Information Engineering Harbin Institute of Technology Harbin China School of Electrical Engineering and Automation Harbin Institute of Technology Harbin China Institute of High Performance Computing A*STAR Singapore Singapore

ISBN: (纸本)9798331509552

The complex permeability of magnetic cores acts as a vital factor in electromagnetic interference (EMI) filtering choke design and optimization. Many efforts have been reported for toroid cores, but fewer target those with other shapes, such as EE, EI, UU, and UI cores. Owing to their commonly used in planar EMI filters, determining the complex permeability of them is of significance. Targeting EE cores, this paper presents a flexible printed circuit board (PCB)-based fixture adapter tailored designed for performing the measurement, while the corresponding core permeability can be calculated through magnetic flux path length analysis. The experiments validate the effectiveness and accuracy of the proposed methods, spanning a wide frequency range up to 120 MHz. ©2024 IEEE.

关键词： Magnetic flux

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Memory access mechanism in embedded real-time Java processor

Memory access mechanism in embedded real-time Java processor

引用

International Conference on computer and Automation engineering, ICCAE

作者： Guang Hu Zhilei Chai Shiliang Tu Department of Computer Science and Engineering Department of Computer Science Shanghai International Studies University Shanghai China Center of Intelligent and High Performance Computing School of Information Technology Jiangnan University Wuxi China Department of Computer Science and Engineering Fudan University Shanghai China

ISBN: (纸本)9781424455690

Currently, Java has been gradually applied in such areas as robotics, industrial control, and other embedded real-time applications owning to its advantages like platform independence, robustness, security, etc. In order to improve the performance of Java's execution engine for embedded real-time applications, an embedded real-time Java processor JPOR-32 (32-bit Java Processor Optimized for RTSJ) is designed. In this paper, the memory access mechanism of JPOR-32 is presented. In JPOR-32, the optimized memory organization structure is designed to implement the runtime data areas of the Java virtual machine (JVM). Based on it, with the preprocessing operation, the memory access instructions optimization is implemented as well. The preprocessing operation enables the JVM's runtime operations involving dynamic loading, verification, preparation, resolution, etc. to be handled in advance. It not only provides an efficient and convenient way to implement memory access, but also makes the contribution to the WCET predictability. As to the memory management, in accordance with the Real-Time Specification for Java (RTSJ), garbage collection (GC) is not allowed in the immortal memory as well as the scoped memory, and in the heap, JPOR-32 adopts improved GC scheme suitable for embedded real-time Java environment. Besides, with the architectural support of the pipelined datapath, JPOR-32 provides effective supports for efficient and predictable memory access.

关键词： Java Memory management Design optimization Runtime Service robots Industrial control Robust control Security Engines Virtual machining

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Hardware support for dynamic activation of compiler-directed computation reuse

Hardware support for dynamic activation of compiler-directed...

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Proceedings of the ninth international conference on Architectural support for programming languages and operating systems

作者： Daniel A. Connors Hillery C. Hunter Ben-Chung Cheng Wen-mei W. Hwu Department of Electrical and Computer Engineering & Computer Science University of Colorado Center for Reliable and High-Performance Computing University of Illinois at Urbana-Champaign Transmeta Corporation Santa Clara CA

ISBN: (纸本)9781581133172

Compiler-directed Computation Reuse (CCR) enhances program execution speed and efficiency by eliminating dynamic computation redundancy. In this approach, the compiler designates large program regions for potential reuse. During run time, the execution results of these reusable regions are recorded into hardware buffers for future reuse. Previous work shows that CCR can result in significant performance enhancements in general applications. A major limitation of the work is that the compiler relies on value profiling to identify reusable regions, making it difficult to deploy the scheme in many software production environments. This paper presents a new hardware model that alleviates the need for value profiling at compile time. The compiler is allowed to designate reusable regions that may prove to be inappropriate. The hardware mechanism monitors the dynamic behavior of compiler-designated regions and selectively activates the profitable ones at run time. Experimental results show that the proposed design makes more effective utilization of hardware buffer resources, achieves rapid employment of computation regions, and improves reuse accuracy, all of which promote more flexible compiler methods of identifying reusable computation regions.

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An enhanced parallel loop self-scheduling scheme for cluster environments

An enhanced parallel loop self-scheduling scheme for cluster...

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International Conference on Advanced Information Networking and Applications (AINA)

作者： Chao-Tung Yang Kuan-Wei Cheng Kuan-Ching Li High-Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung Taiwan Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Taichung Taiwan

ISBN: (纸本)0769522491

In this paper, a parallel loop self-scheduling scheme for heterogeneous PC cluster systems is proposed. Though the proposed scheme does allow users to choose parameters before the execution initialization phase, there are still weaknesses that motivate us to go further with new improvements in that scheme. For instance, a decision on a fixed and monotonous parameter can easily lead to invalid schedule by using previous input information. Thus, it is proposed in this paper a new scheme, where the scheduling parameter can be adjusted dynamically and fit into most widely available computer systems, in order to provide higher overall performance.

关键词： Processor scheduling Dynamic scheduling Load management Master-slave Concurrent computing Distributed computing Clustering algorithms Runtime computer science Scheduling algorithm

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