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Global and localized parallel preconditioning techniques for large scale solid Earth simulations

Global and localized parallel preconditioning techniques for...

引用

International Parallel and Distributed Processing Symposium, IPDPS 2003

作者： Wang, Kai Kim, Sangbae Zhang, Jun Nakajima, Kengo Okuda, Hiroshi Laboratory for High Performance Scientific Computing and Computer Simulation Department of Computer Science University of Kentucky LexingtonKY40506-0046 United States 2-2-54 Naka-Meguro Meguro-ku Tokyo153-0061 Japan Department of Quantum Engineering and System Sciences University of Tokyo 7-3-1 Hongo Bunkyo-ku Tokyo113-8656 Japan

ISBN: (纸本)0769519261

We investigate and compare a few parallel preconditioning techniques in the iterative solution of large sparse linear systems arising from solid Earth simulation with and without using contact information in the domain partitioning process. Previous studies are focused on using static or matrix pattern based incomplete LU (ILU) preconditioners in a localized preconditioner implementation. Our current studies are concerned with preconditioner performance for solving two different cases with and without known contact information. For the cases with contact information, we use localized threshold value based incomplete LU (ILUT) preconditioner to improve efficiency. For the cases without contact information, we use a global sparse approximate inverse preconditioner with a static sparsity pattern to achieve robustness. Numerical results from simulating ground motion on a parallel supercomputer are given to compare the effectiveness of these parallel preconditioning techniques. © 2003 IEEE.

关键词： Linear systems

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Complex Permeability Determination for EE Core Based on Flexible PCB Fixture and Magnetic Flux Path Length Analysis 2

Complex Permeability Determination for EE Core Based on Flex...

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2nd China Power Supply Society Electromagnetic Compatibility Conference, CPEMC 2024

作者： Jie, Huamin Zhao, Zhenyu Chang, Yongqi Wang, Changdong Jiang, Shiqi Gao, Richard Xian-Ke See, Kye Yak School of Electrical and Electronic Engineering Nanyang Technological University Singapore Singapore Department of Electrical and Computer Engineering National Univeristy of Singapore Singapore Singapore Department of Control Science and Engineering Harbin Institute of Technology Harbin China School of Electronics and Information Engineering Harbin Institute of Technology Harbin China School of Electrical Engineering and Automation Harbin Institute of Technology Harbin China Institute of High Performance Computing A*STAR Singapore Singapore

ISBN: (纸本)9798331509552

The complex permeability of magnetic cores acts as a vital factor in electromagnetic interference (EMI) filtering choke design and optimization. Many efforts have been reported for toroid cores, but fewer target those with other shapes, such as EE, EI, UU, and UI cores. Owing to their commonly used in planar EMI filters, determining the complex permeability of them is of significance. Targeting EE cores, this paper presents a flexible printed circuit board (PCB)-based fixture adapter tailored designed for performing the measurement, while the corresponding core permeability can be calculated through magnetic flux path length analysis. The experiments validate the effectiveness and accuracy of the proposed methods, spanning a wide frequency range up to 120 MHz. ©2024 IEEE.

关键词： Magnetic flux

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Memory access mechanism in embedded real-time Java processor

Memory access mechanism in embedded real-time Java processor

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International Conference on computer and Automation engineering, ICCAE

作者： Guang Hu Zhilei Chai Shiliang Tu Department of Computer Science and Engineering Department of Computer Science Shanghai International Studies University Shanghai China Center of Intelligent and High Performance Computing School of Information Technology Jiangnan University Wuxi China Department of Computer Science and Engineering Fudan University Shanghai China

ISBN: (纸本)9781424455690

Currently, Java has been gradually applied in such areas as robotics, industrial control, and other embedded real-time applications owning to its advantages like platform independence, robustness, security, etc. In order to improve the performance of Java's execution engine for embedded real-time applications, an embedded real-time Java processor JPOR-32 (32-bit Java Processor Optimized for RTSJ) is designed. In this paper, the memory access mechanism of JPOR-32 is presented. In JPOR-32, the optimized memory organization structure is designed to implement the runtime data areas of the Java virtual machine (JVM). Based on it, with the preprocessing operation, the memory access instructions optimization is implemented as well. The preprocessing operation enables the JVM's runtime operations involving dynamic loading, verification, preparation, resolution, etc. to be handled in advance. It not only provides an efficient and convenient way to implement memory access, but also makes the contribution to the WCET predictability. As to the memory management, in accordance with the Real-Time Specification for Java (RTSJ), garbage collection (GC) is not allowed in the immortal memory as well as the scoped memory, and in the heap, JPOR-32 adopts improved GC scheme suitable for embedded real-time Java environment. Besides, with the architectural support of the pipelined datapath, JPOR-32 provides effective supports for efficient and predictable memory access.

关键词： Java Memory management Design optimization Runtime Service robots Industrial control Robust control Security Engines Virtual machining

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Hardware support for dynamic activation of compiler-directed computation reuse

Hardware support for dynamic activation of compiler-directed...

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Proceedings of the ninth international conference on Architectural support for programming languages and operating systems

作者： Daniel A. Connors Hillery C. Hunter Ben-Chung Cheng Wen-mei W. Hwu Department of Electrical and Computer Engineering & Computer Science University of Colorado Center for Reliable and High-Performance Computing University of Illinois at Urbana-Champaign Transmeta Corporation Santa Clara CA

ISBN: (纸本)9781581133172

Compiler-directed Computation Reuse (CCR) enhances program execution speed and efficiency by eliminating dynamic computation redundancy. In this approach, the compiler designates large program regions for potential reuse. During run time, the execution results of these reusable regions are recorded into hardware buffers for future reuse. Previous work shows that CCR can result in significant performance enhancements in general applications. A major limitation of the work is that the compiler relies on value profiling to identify reusable regions, making it difficult to deploy the scheme in many software production environments. This paper presents a new hardware model that alleviates the need for value profiling at compile time. The compiler is allowed to designate reusable regions that may prove to be inappropriate. The hardware mechanism monitors the dynamic behavior of compiler-designated regions and selectively activates the profitable ones at run time. Experimental results show that the proposed design makes more effective utilization of hardware buffer resources, achieves rapid employment of computation regions, and improves reuse accuracy, all of which promote more flexible compiler methods of identifying reusable computation regions.

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An enhanced parallel loop self-scheduling scheme for cluster environments

An enhanced parallel loop self-scheduling scheme for cluster...

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International Conference on Advanced Information Networking and Applications (AINA)

作者： Chao-Tung Yang Kuan-Wei Cheng Kuan-Ching Li High-Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung Taiwan Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Taichung Taiwan

ISBN: (纸本)0769522491

In this paper, a parallel loop self-scheduling scheme for heterogeneous PC cluster systems is proposed. Though the proposed scheme does allow users to choose parameters before the execution initialization phase, there are still weaknesses that motivate us to go further with new improvements in that scheme. For instance, a decision on a fixed and monotonous parameter can easily lead to invalid schedule by using previous input information. Thus, it is proposed in this paper a new scheme, where the scheduling parameter can be adjusted dynamically and fit into most widely available computer systems, in order to provide higher overall performance.

关键词： Processor scheduling Dynamic scheduling Load management Master-slave Concurrent computing Distributed computing Clustering algorithms Runtime computer science Scheduling algorithm

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Experimental Verification and Analysis of Dynamic Loop Scheduling in Scientific Applications

Experimental Verification and Analysis of Dynamic Loop Sched...

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International Symposium on Parallel and Distributed computing

作者： Ali Mohammed Ahmed Eleliemy Florina M. Ciorba Franziska Kasielke Ioana Banicescu Department of Mathematics and Computer Science University of Basel Switzerland Center for Information Services and High Performance Computing Technische Universität Dresden Germany Department of Computer Science and Engineering Mississippi State University USA

Scientific applications are often irregular and characterized by large computationally-intensive parallel loops. Dynamic loop scheduling (DLS) techniques improve the performance of computationally-intensive scientific applications via load balancing of their execution on high-performance computing (HPC) systems. Identifying the most suitable choices of data distribution strategies, system sizes, and DLS techniques which improve the performance of a given application, requires intensive assessment and a large number of exploratory native experiments (using real applications on real systems), which may not always be feasible or practical due to associated time and costs. In such cases, simulative experiments are more appropriate for studying the performance of applications. This motivates the question of 'How realistic are the simulations of executions of scientific applications using DLS on HPC platforms?' In the present work, a methodology is devised to answer this question. It involves the experimental verification and analysis of the performance of DLS in scientific applications. The proposed methodology is employed for a computer vision application executing using four DLS techniques on two different HPC platforms, both via native and simulative experiments. The evaluation and analysis of the native and simulative results indicate that the accuracy of the simulative experiments is strongly influenced by the approach used to extract the computational effort of the application (FLOP-or time-based), the choice of application model representation into simulation (data or task parallel) and the available HPC subsystem models in the simulator (multi-core CPUs, memory hierarchy and network topology). The minimum and the maximum percent errors achieved between the native and the simulative experiments are 0.95% and 8.03%, respectively.

关键词： Dynamic scheduling Analytical models Task analysis Computational modeling Power capacitors Processor scheduling

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Modeling of service-level agreements for composed services 13th

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13th IFIP/IEEE International Workshop on Distributed Systems: Operations and Management, DSOM 2002

作者： Daly, David Kar, Gautam Sanders, William H. Center for Reliable and High-Performance Computing Coordinated Science Laboratory and Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign UrbanaIL61801 United States IBM T.J. Watson Research Center P.O.Box 704 Yorktown HeightsNY10598 United States

ISBN: (纸本)3540000801

As Web services are increasingly accepted and used, the next step for them is the development of hierarchical and distributed services that can perform more complex tasks. In this paper, we focus on how to develop guarantees for the performance of an aggregate service based on the guarantees provided by the lower-level services. In particular, we demonstrate the problem with an example of an e-commerce Web site implemented using Web services. The example is based on the Transaction Processing performance Council (TPC) TPC-W Benchmark [8], which specifies an online store complete with a description of all the functionality of the site as well as a description of how customers use the site. We develop models of the site’s performance based on the performance of two sub-services. The model’s results are compared to experimental data and are used to predict the performance of the system under varying conditions. © Springer-Verlag Berlin Heidelberg 2002.

关键词： Web services

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On implementation of an enhanced and integrated parallel programming Web-based toolkit

On implementation of an enhanced and integrated parallel pro...

引用

International Conference on Information Technology: Research and Education (ITRE)

作者： Kuan-Ching Li Chao-Tung Yang Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Taichung Taiwan High Performance Computing Laboratory Department of Computer Science and Infnmation Engineering Tunghai University Taichung Taiwan

ISBN: (纸本)0780389328

The computing power provided by high performance and low cost PC-based clusters and grid computing platforms are attractive and they are equal or superior to supercomputers and mainframes. In parallel, discussions on how to obtain more computing power from these computing platforms become an interesting issue. The development of applications for these high-performance computing platforms is complicated for several reasons: the complexity of applications themselves, which combines aspects of super computing and distributed computing, and by the need to achieve higher performance. This paper describes the design rationale and implementation of a parallel programming Web-based toolkit, to ease the parallel programming learning process, with the use of Web-based interface. The toolkit has widely been used in MPI parallel programming courses (both in graduate and undergraduate levels) and industry trainings.

关键词： Parallel programming Concurrent computing Application software Distributed computing Grid computing high performance computing Visualization computer science Supercomputers Industrial training

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Single pattern search implementations in a cluster computing environment

Single pattern search implementations in a cluster computing...

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Inaugural IEEE-IES Digital EcoSystems and Technologies Conference, DEST

作者： J C Prasad K.S.M. Panicker Department of Computer Science and Engineering Federal Institute of Science and Technology MGR University Chennai Angamaly India Centre of High Performance Computing Federal Institute of Science and Technology Angamaly India

This paper provides an overview of different string matching algorithms in parallel environments. In this work, we have evaluated several algorithms, such as Knuth-Morris-Pratt, Boyer-Moore algorithm, Boyer Moore Horspool Algorithm, Zhu Takaoka algorithm, Quick Search Algorithm, BR Algorithm, Fast Searching algorithm, SSABS algorithm, TVSBS algorithm, ZTMBH algorithm and BRBMH algorithm. Static pattern of string matching algorithms are widely used for searching. For comparisons of speed different algorithms are implemented with parallel programming technique of MPI Standard, for a large text file with a pattern of small length. A Beowulf based homogenous cluster architecture was developed which has a performance of 81 Gigabits floating point operations per second in searching environment. The result of pattern searching showed the variation of performance with this customized cluster architecture for variable number of compute nodes with different pattern lengths. Nearly 80% of the searching code part works in parallel. The performance of string search algorithm is based on the network bandwidth and the selection of algorithms used. Depending on certain applications, different algorithm can be used. It is observed that the cluster searching architecture provides better speed with different algorithms. In general, from the experiments, BRBMH Algorithm is found to be efficient for a general string searching applications.

关键词： Clustering algorithms Signal processing algorithms Algorithm design and analysis computer architecture Complexity theory Program processors Software algorithms

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Decision tree construction for data mining on grid computing environments

Decision tree construction for data mining on grid computing...

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International Conference on Advanced Information Networking and Applications (AINA)

作者： Chao-Tung Yang Shu-Tzu Tsai Kuan-Ching Li High-Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung Taiwan Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Taichung Taiwan

ISBN: (纸本)0769522491

In this paper, the authors presented the grid-based decision tree architecture, with the intention of applying it to both parallel and sequential algorithms. Also, it is shown that, based on the scope and model of data mining applied in the grid environment as well as user equivalent perspective, grid roles can be categorized into three types. It was aimed, through these definitions, to help software developers define clear system processes and differentiate the application scope for software applications. To fulfill the architecture, an existing parallel decision tree algorithm was first applied (the SPRINT algorithm) to the grid environment. The performance and differences in many other areas are compared using datasets of different sizes. The experimental results will be used for future reference and further development.

关键词： Decision trees Data mining Grid computing computer architecture Clustering algorithms Concurrent computing Distributed computing computer science Application software Chaos

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