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检索条件"机构=High Performance Computing Lab Department of Computer Science and Engineering"

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Transfer Learning for Object Detection using State-of-the-Art Deep Neural Networks

Transfer Learning for Object Detection using State-of-the-Ar...

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International Conference on Signal Processing and Integrated Networks (SPIN)

作者： J. Talukdar S. Gupta P. S. Rajpura R. S. Hegde Dept. of Electronics & Communication Engineering Nirma University Ahmedabad Dept. of Computer Engineering & Information Science BITS Pilani Hyderabad Campus High Performance Computing Lab Indian Institute of Technology Gandhinagar

Transfer learning through the use of synthetic images and pretrained convolutional neural networks offers a promising approach to improve the object detection performance of deep neural networks. In this paper, we explore different strategies to generate synthetic datasets and subsequently improve them to achieve better object detection accuracy (mAP) when trained with state-of-the-art deep neural networks, focusing on detection of packed food products in a refrigerator. We develop novel techniques like dynamic stacking, pseudo random placement, variable object pose, distractor noise etc. which not only aid in diversifying the synthetic data but also help in improving the overall object detection mAP by more than 40%. The synthetic images, generated using Blender-Python API, are clustered in a variety of configurations to cater to the diversity of real scenes. These datasets are then utilized to train TensorFlow implementations of state-of-the-art deep neural networks like Faster-RCNN, R-FCN, and SSD and their performance is tested on real scenes. The object detection performance of various deep CNN architectures is also studied, with Faster-RCNN proving to be the most suitable choice, achieving the highest mAP of 70.67.

关键词： Object detection Neural networks Feature extraction Solid modeling Pipelines computer architecture Task analysis

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Harvest rate of reconfigurable pipelines

Harvest rate of reconfigurable pipelines

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： Weiping Shi Ming-Feng Chang W. Kent Fuchs Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Department of Computer Science and Information Engineering National Chiao Tung University Taiwan

Yield analysis for reconfigurable structures is often difficult, due to the defect distribution and irregularity of reconfiguration algorithms. In this paper, the authors give a method to analyze the yield of reconfigurable pipelines for the following model: Given n pipelines with m stages, where each stage of a pipeline is defective with constant probability and spare wires are provided for reconfiguration, the authors calculate the expected percentage of pipelines they can harvest after reconfiguration. By modeling the 'shifting' reconfiguration as weighted chains in a lattice and applying poset theory, they give upper and lower bounds for the harvest rate as a function of m and n.< >

关键词： Pipelines Wires Lattices Very large scale integration Switches Algorithm design and analysis Parallel architectures Supercomputers Equations engineering management

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Programmer Productivity Analyzer Tool

Programmer Productivity Analyzer Tool

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IEEE International Conference on Computational Intelligence and computing Research

作者： Tejaswini Srushti Patil Suman Salimath Venuprasad Naik Ritam Nandi Mahesh S. Patil Indira Bidari Satyadhyan Chickerur Department of Computer Science and Engineering B.V.B.College of Engineering and Technology K L E Technological University Centre for High Performance Computing Hubballi Karnataka 580 031 INDIA

Software companies seek for productive programmer who writes codes that are reusable, maintainable, efficient and documented with coding standards. But companies face challenges in finding and monitoring such programmers due to lack of programmer productivity measuring tools. The available tools are limited to measure parameters like coding standards, bugs and some rule violation. Hence there is need for tools that can measure bad programming constructs, reusability and specific demands of companies in coding to judge a programmer. This paper proposes a novel method and tool to measure programmer productivity based on parameters such as efficient usage of memory and machine cycles. It also assist programmer to improve their productivity. The tool is able to detect 3-4 types and 1-2 types of bad programming constructs in code written by novices and experienced programmers respectively. In future, the tool shall be designed to measure the productivity using other parameters reusability and maintainable.

关键词： Productivity Tools Programming Encoding Standards Companies computer bugs

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Parallel algorithms for simultaneous scheduling, binding and floorplanning in high-level synthesis

Parallel algorithms for simultaneous scheduling, binding and...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： P. Prabhakaran P. Banerjee Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign IL USA Center for Parallel and Distributed Computing Department of Electrical and Computer Engineering Northwestern University Evanston IL USA

With small device features in submicron technologies, interconnection delays play a dominant part in cycle time. Hence, it is important to consider the impact of physical design during high level synthesis. In comparison to a traditional approach which separates high-level synthesis from physical design, an algorithm which is able to make these stages interact very closely, would result in solutions with lower latency and area. However, such an approach could result in increased runtimes. Parallel processing is an attractive way of reducing the runtimes. In this paper, two parallel algorithms for simultaneous scheduling, binding and floorplanning algorithm are presented. A detailed hardware model is considered, taking into account multiplexor and register areas and delays. Experimental results are reported on an IBM SP-2 multicomputer, with close to linear speedups for a set of benchmark circuits.

关键词： Parallel algorithms high level synthesis Runtime Integrated circuit interconnections Delay effects Algorithm design and analysis Parallel processing Scheduling algorithm Hardware Registers

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HAPIC: A Scalable, Lightweight and Reactive Cache for Persistent-Memory-Based Index

HAPIC: A Scalable, Lightweight and Reactive Cache for Persis...

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IEEE International Conference on computer-Aided Design

作者： Chih-Ting Lo Yun-Chih Chen Yuan-Hao Chang Tei-Wei Kuo Department of Computer Science and Information Engineering National Taiwan University Academia Sinica Institute of Information Science Taiwan Department of Computer Science Mohamed bin Zayed University of Artificial Intelligence NTU High Performance and Scientific Computing Center National Taiwan University

In-memory index delivers low-latency responses for data services. It has been ported to high-capacity persistent memory (PM) to accommodate more data. However, read-heavy, extremely-skewed, and highly-dynamic workloads can suffer from degraded performance on PM-based indexes. We present HAPIC, a scalable cache over PM-based indexes to capture the constantly-changing query hotspots in skewed workloads. HAPIC embodies the data access frequency gradient in a hierarchy of hash tables to efficiently identify hotspots and reacts quickly to workload changes with epoch-based promotion. Compared with the state-of-the-art strategy, HAPIC reacts to hotspot shifts significantly faster, with up to 14% higher stable read throughput, 26% lower median latency, and 13% lower P99 latency.

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Scaling communication-intensive applications on BlueGene/P using one-sided communication and overlap

Scaling communication-intensive applications on BlueGene/P u...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Rajesh Nishtala Paul H. Hargrove Dan O. Bonachea Katherine A. Yelick Computer Science Division College of Engineering University of California Berkeley Berkeley CA USA High Performance Computing Research Department Lawrence Berkeley National Laboratory Berkeley CA USA

In earlier work, we showed that the one-sided communication model found in PGAS languages (such as UPC) offers significant advantages in communication efficiency by decoupling data transfer from processor synchronization. We explore the use of the PGAS model on IBM BlueGene/P, an architecture that combines low-power, quad-core processors with extreme scalability. We demonstrate that the PGAS model, using a new port of the Berkeley UPC compiler and GASNet one-sided communication layer, outperforms two-sided (MPI) communication in both microbenchmarks and a case study of the communication-limited benchmark, NAS FT. We scale the benchmark up to 16, 384 cores of the BlueGene/P and demonstrate that UPC consistently outperforms MPI by as much as 66% for some processor configurations and an average of 32%. In addition, the results demonstrate the scalability of the PGAS model and the Berkeley implementation of UPC, the viability of using it on machines with multicore nodes, and the effectiveness of the BG/P communication layer for supporting one-sided communication and PGAS languages.

关键词： Electronics packaging Scalability high performance computing Power system modeling Parallel processing Large-scale systems Yarn Read-write memory Application software computer science

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APP: Enabling Soft Real-Time Execution on Densely-Populated Hybrid Memory System

APP: Enabling Soft Real-Time Execution on Densely-Populated ...

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Design Automation Conference

作者： Zheng-Wei Wu Yun-Chih Chen Yuan-Hao Chang Tei-Wei Kuo Department of Computer Science and Information Engineering National Taiwan University Institute of Information Science Academia Sinica Taiwan Department of Computer Science Mohamed bin Zayed University of Artificial Intelligence NTU High Performance and Scientific Computing Center National Taiwan University

Memory swapping was considered slow and evil, but swapping to Ultra Low-Latency storage like Optane has become a promising solution to save power and cost, helping densely-populated edge server to overcome its DRAM capacity bottleneck. However, the lack of integration between CPU scheduling and memory paging causes soft real-time tasks running on edge servers to miss deadlines under heavy memory multiplexing. We propose APP (Adaptive Page Pinning), lightweight protection of working set memory to ensure meeting soft real-time task deadlines without starving other non-real-time tasks. Experiments show that APP alleviates thrashing in memory-intensive tasks and upholds soft real-time task deadlines.

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A Heuristic Sparsification Method to Improve the performance of Neural Networks on Autism Spectrum Disorder Identification Tasks 13

A Heuristic Sparsification Method to Improve the Performance...

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13th International Conference on Information science and Technology, ICIST 2023

作者： Zhang, Fangyu Wei, Yanjie Lin, Zhenli Pan, Yi Liu, Jin Centre for High Performance Computing Shenzhen Institute of Advanced Technology Chinese Academy of Sciences Shenzhen China Department of Ophthalmology Shenzhen University General Hospital Shenzhen China Shenzhen Key Laboratory of Intelligent Bioinformatics Shenzhen Institute of Advanced Technology Chinese Academy of Sciences Shenzhen China School of Computer Science and Engineering Central South University Changsha China

ISBN: (纸本)9798350313925

Deep learning (DL) has been widely used in the detection of neurological diseases such as Autism spectrum disorder (ASD). Most studies in this field manually designed and adjusted the hyperparameters of DL models, but due to the huge search space, few studies have attempted to optimize the topology of neural networks which is another important factor related to the performance of DL models. This paper proposes a heuristic sparsification method named the Evolutionary Connection Sparsification Algorithm (ECSA) which is used to optimize the topology of fully connected neural networks (FC-NNs) and generate the corresponding sparsely connected neural networks (SC-NNs). The algorithm is based on the workflow of the genetic algorithm but with improved coding strategy, fitness evaluation approach, crossover and mutation operator, and including an effective convergence acceleration strategy. Experiments show that the SC-NNs generated by ECSA significantly outperform the original FC-NNs in terms of accuracy, F1-score, and AUC, and the model complexities are greatly reduced. © 2023 IEEE.

关键词： Topology

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Evaluating the Flexibility of Dynamic Loop Scheduling on Heterogeneous Systems in the Presence of Fluctuating Load Using SimGrid

Evaluating the Flexibility of Dynamic Loop Scheduling on Het...

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IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Nitin Sukhija Ioana Banicescu Srishti Srivastava Florina M. Ciorba Department of Computer Science and Engineering Mississippi State University Mississippi State MS USA Technische Universität Dresden Center for Information Services and High Performance Computing Dresden Germany

ISBN: (纸本)9781479913725

Scientific applications running on heterogeneous computing systems, which often have unpredictable behavior, enhance their performance by employing loop scheduling techniques as methods to avoid load imbalance through an optimized assignment of their parallel loops. With current computing platforms facilitating petascale performance and promising exascale performance towards the end of the present decade, efficient and robust algorithms are required to guarantee optimal performance of parallel applications in the presence of unpredictable perturbations. A number of dynamic loop scheduling (DLS) methods based on probabilistic analyses have been developed to achieve the desired robust performance. In earlier work, two metrics (flexibility and resilience) have been formulated to quantify the robustness of various DLS methods in heterogeneous computing systems with uncertainties. In this work, to ensure robust performance of the scientific applications on current (petascale) and future(exascale) high performance computing systems, a simulation model was designed and integrated into the SimGrid simulation toolkit, thus enabling a comprehensive study of the robustness of the DLS methods which uses results of experimental cases with various combinations of number of processors, problem sizes, and scheduling methods. The DLS methods have been implemented into the simulation model and analyzed for the purpose of exploring their flexibility (robustness against unpredictable variations in the system load), when involved in a range of case scenarios comprised of various distributions characterizing loop iteration execution times and system availability. The simulation results reported are used to compare the robustness of the DLS methods under the various environments considered, using the flexibility metric.

关键词： Robustness Program processors Computational modeling Availability Processor scheduling Load modeling Measurement

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Proteus: a flexible infrastructure to implement adaptive fault tolerance in AQuA

Proteus: a flexible infrastructure to implement adaptive fau...

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Dependable computing for Critical Applications 7

作者： C. Sabnis M. Cukier J. Ren P. Rubel W.H. Sanders D.E. Bakken D. Karr Center of Reliable and High-Performance Computing Coordinated Science Laboratory and Department of Electrical and Computer Engineering University of Illinois Urbana IL USA BBN Technologies GTE Cambridge MA USA

Building dependable distributed systems from commercial off-the-shelf components is of growing practical importance. For both cost and production reasons, there is interest in approaches and architectures that facilitate building such systems. The AQuA architecture is one such approach; its goal is to provide adaptive fault tolerance to CORBA applications by replicating objects, providing a high-level method for applications to specify their desired dependability, and providing a dependability manager that attempts to reconfigure a system at runtime so that dependability requests are satisfied. This paper describes how dependability is provided in AQuA. In particular it describes Proteus, the part of AQuA that dynamically manages replicated distributed objects to make them dependable. Given a dependability request, Proteus chooses a fault tolerance approach and reconfigures the system to try to meet the request. The infrastructure of Proteus is described in this paper, along with its use in implementing active replication and a simple dependability policy.

关键词： Fault tolerance Quality of service Buildings Application software Costs Fault tolerant systems Hardware Contracts Distributed computing high performance computing

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