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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Rajesh Nishtala Paul H. Hargrove Dan O. Bonachea Katherine A. Yelick Computer Science Division College of Engineering University of California Berkeley Berkeley CA USA High Performance Computing Research Department Lawrence Berkeley National Laboratory Berkeley CA USA

In earlier work, we showed that the one-sided communication model found in PGAS languages (such as UPC) offers significant advantages in communication efficiency by decoupling data transfer from processor synchronization. We explore the use of the PGAS model on IBM BlueGene/P, an architecture that combines low-power, quad-core processors with extreme scalability. We demonstrate that the PGAS model, using a new port of the Berkeley UPC compiler and GASNet one-sided communication layer, outperforms two-sided (MPI) communication in both microbenchmarks and a case study of the communication-limited benchmark, NAS FT. We scale the benchmark up to 16, 384 cores of the BlueGene/P and demonstrate that UPC consistently outperforms MPI by as much as 66% for some processor configurations and an average of 32%. In addition, the results demonstrate the scalability of the PGAS model and the Berkeley implementation of UPC, the viability of using it on machines with multicore nodes, and the effectiveness of the BG/P communication layer for supporting one-sided communication and PGAS languages.

关键词： Electronics packaging Scalability high performance computing Power system modeling Parallel processing Large-scale systems Yarn Read-write memory Application software computer science

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APP: Enabling Soft Real-Time Execution on Densely-Populated Hybrid Memory System

APP: Enabling Soft Real-Time Execution on Densely-Populated ...

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Design Automation Conference

作者： Zheng-Wei Wu Yun-Chih Chen Yuan-Hao Chang Tei-Wei Kuo Department of Computer Science and Information Engineering National Taiwan University Institute of Information Science Academia Sinica Taiwan Department of Computer Science Mohamed bin Zayed University of Artificial Intelligence NTU High Performance and Scientific Computing Center National Taiwan University

Memory swapping was considered slow and evil, but swapping to Ultra Low-Latency storage like Optane has become a promising solution to save power and cost, helping densely-populated edge server to overcome its DRAM capacity bottleneck. However, the lack of integration between CPU scheduling and memory paging causes soft real-time tasks running on edge servers to miss deadlines under heavy memory multiplexing. We propose APP (Adaptive Page Pinning), lightweight protection of working set memory to ensure meeting soft real-time task deadlines without starving other non-real-time tasks. Experiments show that APP alleviates thrashing in memory-intensive tasks and upholds soft real-time task deadlines.

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A Heuristic Sparsification Method to Improve the performance of Neural Networks on Autism Spectrum Disorder Identification Tasks 13

A Heuristic Sparsification Method to Improve the Performance...

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13th International Conference on Information science and Technology, ICIST 2023

作者： Zhang, Fangyu Wei, Yanjie Lin, Zhenli Pan, Yi Liu, Jin Centre for High Performance Computing Shenzhen Institute of Advanced Technology Chinese Academy of Sciences Shenzhen China Department of Ophthalmology Shenzhen University General Hospital Shenzhen China Shenzhen Key Laboratory of Intelligent Bioinformatics Shenzhen Institute of Advanced Technology Chinese Academy of Sciences Shenzhen China School of Computer Science and Engineering Central South University Changsha China

ISBN: (纸本)9798350313925

Deep learning (DL) has been widely used in the detection of neurological diseases such as Autism spectrum disorder (ASD). Most studies in this field manually designed and adjusted the hyperparameters of DL models, but due to the huge search space, few studies have attempted to optimize the topology of neural networks which is another important factor related to the performance of DL models. This paper proposes a heuristic sparsification method named the Evolutionary Connection Sparsification Algorithm (ECSA) which is used to optimize the topology of fully connected neural networks (FC-NNs) and generate the corresponding sparsely connected neural networks (SC-NNs). The algorithm is based on the workflow of the genetic algorithm but with improved coding strategy, fitness evaluation approach, crossover and mutation operator, and including an effective convergence acceleration strategy. Experiments show that the SC-NNs generated by ECSA significantly outperform the original FC-NNs in terms of accuracy, F1-score, and AUC, and the model complexities are greatly reduced. © 2023 IEEE.

关键词： Topology

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Evaluating the Flexibility of Dynamic Loop Scheduling on Heterogeneous Systems in the Presence of Fluctuating Load Using SimGrid

Evaluating the Flexibility of Dynamic Loop Scheduling on Het...

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IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Nitin Sukhija Ioana Banicescu Srishti Srivastava Florina M. Ciorba Department of Computer Science and Engineering Mississippi State University Mississippi State MS USA Technische Universität Dresden Center for Information Services and High Performance Computing Dresden Germany

ISBN: (纸本)9781479913725

Scientific applications running on heterogeneous computing systems, which often have unpredictable behavior, enhance their performance by employing loop scheduling techniques as methods to avoid load imbalance through an optimized assignment of their parallel loops. With current computing platforms facilitating petascale performance and promising exascale performance towards the end of the present decade, efficient and robust algorithms are required to guarantee optimal performance of parallel applications in the presence of unpredictable perturbations. A number of dynamic loop scheduling (DLS) methods based on probabilistic analyses have been developed to achieve the desired robust performance. In earlier work, two metrics (flexibility and resilience) have been formulated to quantify the robustness of various DLS methods in heterogeneous computing systems with uncertainties. In this work, to ensure robust performance of the scientific applications on current (petascale) and future(exascale) high performance computing systems, a simulation model was designed and integrated into the SimGrid simulation toolkit, thus enabling a comprehensive study of the robustness of the DLS methods which uses results of experimental cases with various combinations of number of processors, problem sizes, and scheduling methods. The DLS methods have been implemented into the simulation model and analyzed for the purpose of exploring their flexibility (robustness against unpredictable variations in the system load), when involved in a range of case scenarios comprised of various distributions characterizing loop iteration execution times and system availability. The simulation results reported are used to compare the robustness of the DLS methods under the various environments considered, using the flexibility metric.

关键词： Robustness Program processors Computational modeling Availability Processor scheduling Load modeling Measurement

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Proteus: a flexible infrastructure to implement adaptive fault tolerance in AQuA

Proteus: a flexible infrastructure to implement adaptive fau...

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Dependable computing for Critical Applications 7

作者： C. Sabnis M. Cukier J. Ren P. Rubel W.H. Sanders D.E. Bakken D. Karr Center of Reliable and High-Performance Computing Coordinated Science Laboratory and Department of Electrical and Computer Engineering University of Illinois Urbana IL USA BBN Technologies GTE Cambridge MA USA

Building dependable distributed systems from commercial off-the-shelf components is of growing practical importance. For both cost and production reasons, there is interest in approaches and architectures that facilitate building such systems. The AQuA architecture is one such approach; its goal is to provide adaptive fault tolerance to CORBA applications by replicating objects, providing a high-level method for applications to specify their desired dependability, and providing a dependability manager that attempts to reconfigure a system at runtime so that dependability requests are satisfied. This paper describes how dependability is provided in AQuA. In particular it describes Proteus, the part of AQuA that dynamically manages replicated distributed objects to make them dependable. Given a dependability request, Proteus chooses a fault tolerance approach and reconfigures the system to try to meet the request. The infrastructure of Proteus is described in this paper, along with its use in implementing active replication and a simple dependability policy.

关键词： Fault tolerance Quality of service Buildings Application software Costs Fault tolerant systems Hardware Contracts Distributed computing high performance computing

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Building dependable distributed applications using AQUA

Building dependable distributed applications using AQUA

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IEEE International Symposim on high Assurance Systems engineering

作者： J. Ren M. Cukier P. Rubel W.H. Sanders D.E. Bakken D.A. Karr Center for Reliable and High-Performance Computing Coordinated Science Laboratory and Department of Electrical and Computer Engineering University of Illinois Urbana IL USA BBN Technologies GTE Cambridge MA USA

Building dependable distributed systems using ad hoc methods is a challenging task. Without proper support, an application programmer must face the daunting requirement of having to provide fault tolerance at the application level, in addition to dealing with the complexities of the distributed application itself. This approach requires a deep knowledge of fault tolerance on the part of the application designer, and has a high implementation cost. What is needed is a systematic approach to providing dependability to distributed applications. Proteus, part of the AQuA architecture, fills this need and provides facilities to make a standard distributed CORBA application dependable, with minimal changes to an application. Furthermore, it permits applications to specify, either directly or via the Quality Objects (QuO) infrastructure, the level of dependability they expect of a remote object, and will attempt to configure the system to achieve the requested dependability level. Our previous papers have focused on the architecture and implementation of Proteus. This paper describes how to construct dependable applications using the AQuA architecture, by describing the interface that a programmer is presented with and the graphical monitoring facilities that it provides.

关键词： Electrical capacitance tomography Fault tolerance Buildings Application software Quality of service Contracts Hardware Runtime Object detection Tellurium

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Leveraging performance Counters and Execution Logs to Diagnose Memory-Related performance Issues

Leveraging Performance Counters and Execution Logs to Diagno...

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International Conference on Software Maintenance (ICSM)

作者： Mark D. Syer Zhen Ming Jiang Meiyappan Nagappan Ahmed E. Hassan Mohamed Nasser Parminder Flora Software Analysis and Intelligence Lab Queen's University Canada Department of Electrical Engineering & Computer Science York University Canada Performance Engineering School of Computing BlackBerry Canada

Load tests ensure that software systems are able to perform under the expected workloads. The current state of load test analysis requires significant manual review of performance counters and execution logs, and a high degree of system-specific expertise. In particular, memory-related issues (e.g., memory leaks or spikes), which may degrade performance and cause crashes, are difficult to diagnose. performance analysts must correlate hundreds of megabytes or gigabytes of performance counters (to understand resource usage) with execution logs (to understand system behaviour). However, little work has been done to combine these two types of information to assist performance analysts in their diagnosis. We propose an automated approach that combines performance counters and execution logs to diagnose memory-related issues in load tests. We perform three case studies on two systems: one open-source system and one large-scale enterprise system. Our approach flags ≤ 0.1% of the execution logs with a precision ≥ 80%.

关键词： Radiation detectors Standards Transient analysis Lifting equipment Memory management Couplings Visualization

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MAPA: Multi-accelerator pattern allocation policy for multi-tenant GPU servers

arXiv

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arXiv 2021年

作者： Ranganath, Kiran Suetterlein, Joshua D. Manzano, Joseph B. Song, Shuaiwen Leon Wong, Daniel Department of Electrical and Computer Engineering University of California RiversideCA United States High-Performance Computing Group Pacific Northwest National Lab WA United States Future System Architecture Lab School of Computer Science University of Sydney SydneyNSW Australia

Multi-accelerator servers are increasingly being deployed in shared multi-tenant environments (such as in cloud data centers) in order to meet the demands of large-scale compute-intensive workloads. In addition, these accelerators are increasingly being inter-connected in complex topologies and workloads are exhibiting a wider variety of inter-accelerator communication patterns. However, existing allocation policies are ill-suited for these emerging use-cases. Specifically, this work identifies that multi-accelerator workloads are commonly fragmented leading to reduced bandwidth and increased latency for inter-accelerator communication. We propose Multi-Accelerator Pattern Allocation (MAPA), a graph pattern mining approach towards providing generalized allocation support for allocating multi-accelerator workloads on multi-accelerator servers. We demonstrate that MAPA is able to improve the execution time of multi-accelerator workloads and that MAPA is able to provide generalized benefits across various accelerator topologies. Finally, we demonstrate a speedup of 12.4% for 75th percentile of jobs with the worst case execution time reduced by up to 35% against baseline policy using MAPA. © 2021, CC BY-NC-SA.

关键词： Graphics processing unit

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Data mining analysis to validate performance tuning practices for HPL

Data mining analysis to validate performance tuning practice...

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IEEE International Conference on Cluster computing

作者： Tuan Zea Tan Rick Siow Mong Goh Verdi March Simon See Institute of High Performance Computing Advanced Computing Singapore Asia-Pacific Science & Technology Center Sun MicroSystems Inc. India Department of Computer Science National University of Singapore Singapore Department of Mechanical & Aerospace Engineering Nanyang Technological University Singapore

Applications performance is a criterion for system evaluation, and hence performance tuning for these applications is of great interest. One such benchmark application is high performance Linpack (HPL). Although guidelines exist for HPL tuning, validating these guidelines on various systems is a challenging task as a large number of configurations need to be tested. In this work, we use data mining analysis to reduce the number of configurations to be tested in validating the HPL tuning guidelines on the Ranger System. We validate that NB, P and Q are the three most important parameters to tune HPL, and that PMAP does not have a significant impact on HPL performance. We also validate the practice of tuning HPL at small N using data mining analysis. We find that the value of N selected for tuning should not be significantly smaller than the largest N that can fit into the system memory. Our results indicate that data mining could be further applied to application performance tuning.

关键词： Data mining Data analysis performance analysis Application software Guidelines Benchmark testing Analytical models Thumb high performance computing Niobium

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SymSig: A low latency interconnection topology for HPC clusters

SymSig: A low latency interconnection topology for HPC clust...

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International Conference on high performance computing

作者： Dhananjay Brahme Onkar Bhardwaj Vipin Chaudhary High Performance Computing Center of Excellence Tata Consultancy Services Pune India Department of Electrical Rensselaer Polytechnic Institute Troy NY Department of Computer Science and Engineering SUNY Buffalo New York

This paper presents the underlying theory and the performance of a cluster using a new 2-hop network topology. This topology is constructed using a symmetric equation and Singer Difference Sets and is called SymSig. The degree of connections at each node with SymSig is about half compared to previous methods using Singer Difference Sets. A comparison with a cluster of Clos topology shows significant advantages. The worst case congestion in SymSig topology for unicast permutation is 2, where as in Clos it is proportional to the radix of the building block switches used. The number of switches required is smaller by about 25%, the size of the cluster is larger by about 15% and the worst bandwidth is better by about 50% for SymSig. These advantages are retained for peta and exascale systems. Its performance on a set of collectives like exchange-all, shift-all, broadcast-all and all-to-all send/receive shows improvements ranging from 39% to 83%. Its performance on a molecular dynamics application GROMMACS shows improvement of upto 33%. This network is particularly suitable for applications that require global all to all communications. The low latency of this network makes it scaleable and an attractive alternative for building peta and exascale systems.

关键词： Routing Image color analysis Topology Network topology Ports (computers) Equations Bandwidth

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