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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： P. Prabhakaran P. Banerjee Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign IL USA Center for Parallel and Distributed Computing Department of Electrical and Computer Engineering Northwestern University Evanston IL USA

With small device features in submicron technologies, interconnection delays play a dominant part in cycle time. Hence, it is important to consider the impact of physical design during high level synthesis. In comparison to a traditional approach which separates high-level synthesis from physical design, an algorithm which is able to make these stages interact very closely, would result in solutions with lower latency and area. However, such an approach could result in increased runtimes. Parallel processing is an attractive way of reducing the runtimes. In this paper, two parallel algorithms for simultaneous scheduling, binding and floorplanning algorithm are presented. A detailed hardware model is considered, taking into account multiplexor and register areas and delays. Experimental results are reported on an IBM SP-2 multicomputer, with close to linear speedups for a set of benchmark circuits.

关键词： Parallel algorithms high level synthesis Runtime Integrated circuit interconnections Delay effects Algorithm design and analysis Parallel processing Scheduling algorithm Hardware Registers

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AQuA: an adaptive architecture that provides dependable distributed objects

AQuA: an adaptive architecture that provides dependable dist...

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Reliable Distributed Systems

作者： M. Cukier J. Ren C. Sabnis D. Henke J. Pistole W.H. Sanders D.E. Bakken M.E. Berman D.A. Karr R.E. Schantz Center for Reliable and High-Performance Computing Coordinated Science Laboratory and Electrical and Computer Engineering Department University of Illinois Urbana-Champaign Urbana IL USA BBN Technologies Inc. Cambridge MA USA

Dependable distributed systems are difficult to build. This is particularly true if they have dependability requirements that change during the execution of an application, and are built with commercial off-the-shelf hardware. In that case, fault tolerance must be achieved using middleware software, and mechanisms must be provided to communicate the dependability requirements of a distributed application to the system and to adapt the system's configuration to try to achieve the desired dependability. The AQuA architecture allows distributed applications to request a desired level of availability using the Quality Objects (QuO) framework and includes a dependability manager that attempts to meet requested availability levels by configuring the system in response to outside requests and changes in system resources due to faults. The AQuA architecture uses the QuO runtime to process and invoke availability requests, the Proteus dependability manager to configure the system in response to faults and availability requests, and the Ensemble protocol stack to provide group communication services. Furthermore, a CORBA interface is provided to application objects using the AQuA gateway. The gateway provides a mechanism to translate between process-level communication, as supported by Ensemble, and IIOP messages, understood by Object Request Brokers. Both active and passive replication are supported, and the replication type to use is chosen based on the performance and dependability requirements of particular distributed applications.

关键词： Availability Application software computer architecture Hardware Fault tolerant systems Middleware Communication system software Quality management Resource management Runtime

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Graph visualization for the analysis of the structure and dynamics of extreme-scale supercomputers

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Information Visualization 1997年第3期3卷 209-222页

作者： Summers, Kenneth L. Caudell, Thomas Preston Berkbigler, Kathryn Bush, Brian Davis, Kei Smith, Steve Center for High Performance Computing University of New Mexico Albuquerque NM United States Department of Electrical & Computer Engineering University of New Mexico Albuquerque NM United States Los Alamos National Laboratory Los Alamos NM United States

We are exploring the development and application of information visualization techniques for the analysis of new massively parallel supercomputer architectures. Modern supercomputers typically comprise very large clusters of commodity SMPs interconnected by possibly dense and often non-standard networks. The scale, complexity, and inherent non-locality of the structure and dynamics of this hardware, and the operating systems and applications distributed over them, challenge traditional analysis methods. As part of the á la carte (A Los Alamos computer Architecture Toolkit for Extreme-Scale Architecture Simulation) team at Los Alamos National laboratory, who are simulating these new architectures, we are exploring advanced visualization techniques and creating tools to enhance analysis of these simulations with intuitive three-dimensional representations and interfaces. This work complements existing and emerging algorithmic analysis tools. In this paper, we give background on the problem domain, a description of a prototypical computer architecture of interest (on the order of 10,000 processors connected by a quaternary fat-tree communications network), and a presentation of three classes of visualizations that clearly display the switching fabric and the flow of information in the interconnecting network. © 2004, SAGE Publications. All rights reserved.

关键词： graph visualization scalable representations virtual environments

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Parallel computing on SCSI network

Parallel computing on SCSI network

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IEEE National Conference on Aerospace and Electronics (NAECON)

作者： G.H. Young V.S. Yiu Lai-Man Wan High Performance Computer Laboratory Department of Computer Science and Engineering Chinese University of Hong Kong Sha Tin Hong Kong China High Performance Computing Laboratory Department of Computer Science and Engineering Chinese University of Hong Kong Sha Tin Hong Kong China

Different architectures of multicomputers have emerged rapidly in the last two decades. In this paper, we present the implementation of a network parallel system using the homogeneous Unix machines on SCSI networks. The system is different from the traditional systems in that we applied general purpose peripheral buses to connect the workstations. In this paper, we discuss the low level operations of the interconnecting network and the isomorphic property of SCSI.

关键词： Parallel processing Workstations Hardware Costs Communication system control high performance computing Laboratories computer science computer architecture Communication system software

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A lifetime-sensitive scheduling method

A lifetime-sensitive scheduling method

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Proceedings of the Advances in Parallel and Distributed computing

作者： Xinda Lu Yi Hu Jie Chen High Performance Computing Lab Department of Computer Science and Engineering Shanghai Jiaotong University Shanghai China

ISBN: (纸本)0818678763

This paper presents a lifetime-sensitive scheduling method. By shortening lifetimes of variables in scheduling phase, it can lighten register pressure in register allocation phase, lessen spill codes and result in more efficient object codes. The preliminary experimental results show that this method is an effective scheduling method.

关键词： Costs Processor scheduling Optimizing compilers Registers Parallel processing high performance computing computer science Reduced instruction set computing Upper bound performance evaluation

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Java Message Passing Interface

Java Message Passing Interface

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IEEE National Conference on Aerospace and Electronics (NAECON)

作者： G.H. Young Lai-Man Wan V.S. Yiu High Performance Computing Laboratory Department of Computer Science and Engineering Chinese University of Hong Kong Sha Tin Hong Kong China

The emergence of World Wide Web and Java technologies has altered the view of the Internet. It provides an open standard interface among the heterogeneous computers on the Internet. To exploit the enormous computational resources on the Internet, we have developed a Java-based parallel programming environment called Java Message Passing Interface (JMPI). It runs on different machines regardless of their computer architecture or operating systems. It uses arbitrary machines on the Internet as computation nodes, and provides an application programming interface which follows the semantic of Message Passing Interface standard. In this paper, we present the overview of the infrastructure of this parallel programming environment.

关键词： Java Message passing Internet computer interfaces Parallel programming Web sites Concurrent computing computer architecture Operating systems Application software

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A secure communications infrastructure for high-performance distributed computing 97

A secure communications infrastructure for high-performance ...

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International Symposium on high performance Distributed computing

作者： I. Foster N.T. Karonis C. Kesselman G. Koenig S. Tuecke Mathematics and Computer Science Argonne National Laboratory Argonne IL USA High-Performance Computing Laboratory Department of Computer Science Northern Illinois University DeKalb IL USA Information Sciences Institute University of Southern California Marina Del Rey CA USA

ISBN: (纸本)9780818681172

Applications that use high-speed networks to connect geographically distributed supercomputers, databases, and scientific instruments may operate over open networks and access valuable resources. Hence, they can require mechanisms for ensuring integrity and confidentiality of communications and for authenticating both users and resources. Security solutions developed for traditional client-server applications do not provide direct support for the program structures, programming tools, and performance requirements encountered in these applications. We address these requirements via a security-enhanced version of the Nexus communication library, which we use to provide secure versions of parallel libraries and languages, including the Message Passing Interface. These tools permit a fine degree of control over what, where, and when security mechanisms are applied. In particular, a single application can mix secure and nonsecure communication allowing the programmer to make fine-grained security/performance tradeoffs. We present performance results that quantify the performance of our infrastructure.

关键词： Distributed computing Data security Supercomputers Instruments Libraries computer science Laboratories Application software high-speed networks Distributed databases

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Using ZPL to develop a parallel chaos router simulator 96

Using ZPL to develop a parallel chaos router simulator

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1996 Winter Simulation Conference (WSC 96)

作者： Richardson, W Bailey, ML Sanders, WH Department of Electrical and Computer Engineering University of Arizona Tucson AZ Computer Science Department University of Arizona Tucson AZ Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois at Urbana-Champaign Urbana IL

ISBN: (纸本)0780333837

This paper reports on our experience in writing a parallel version of a chaos router simulator using the new data-driven parallel language ZPL. The simulator is a large program that tests the capabilities of ZPL. The (parallel) ZPL program is compared with the existing serial implementation on two very different architectures: a 16-processor Intel Paragon and a cluster of eight Alpha workstations. On the Paragon, the simulator performs best when simulating medium- to large-sized routers, and on the Alpha cluster, it performs best when simulating large routers. Thus a user can choose the parallel platform best suited to the router size.

关键词： Parallel processing systems

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Operational systems, logistics engineering and technology insertion

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NAVAL ENGINEERS JOURNAL 1997年第3期109卷 205-220页

作者： Grubb, MJ Skolnick, A Michael J. Grubb:has perfomzed naval engineering at the Crane Division Naval Surface Warfare Center (NSWC) for more than twenty-five years. He currently the program manager for the Sustainable Hardware and Affordable Readiness Practice Program (SHARP). is a Navy-wide logistics research and development prgram aimed at the successful transiton of proved technologies inot the fleet. SHARP focuses on reducing acquisition performance capability reliability maintainability and readiness of these systems. Mr. Grubb has served as a department director for the past eleven years. His most recent assignment was as director of the Tactical Computer Resources and Test Equipment Department. This organization provided acquisition and in-service engineering support of the Navy's tectical embedded computers priphirals displays and mass memory storage devices. The organization also provided a complete range of product engineering and metrology engineerig services for SSP NevSeaSysCom and the Trident Program. Prior to this appointment Mr. Grubb was deptuy director psysical security programs department and site responsible for program management and system integration of ashore integrated security systems. Mr. Grubb holds a B.S. degree in industrial engineering from Iowa State Universtiy an M.S. degree in industrial engineering from Purdue University and has copleted the course work (Dec.'96 for a master's degree in public and environment affairs at Indiana University-Purdue Univeristy Indianapolis. Dr. Alfred Skolnick operates System Science Consultants (SSC) specilizing in strategic planning technical program definiton technology assessment and engineering analyses on selected matters of national interest. He has taught physics mathematics and management sciences at University of Virginia and Marymount University and is currently adjunct professor of mathematics at Northern Virginia Community College. Form 1985 to 1989 he was president of the American Society of Noval Engineers. Dr. Skolnick served at Applied Physic

In an era of fiscal austerity, downsizing and unforgiving pressure upon human and economic capital, it is an Augean task to identify resources for fresh and creative work. The realities of the day and the practical demands of more immediate fleet needs can often dictate higher priorities. Yet, the Navy must avoid eating its seed corn. Exercising both technical insight and management foresight, the fleet, the R&D community, the Office of the Chief of Naval Operations (OpNav) and the product engineering expertise of the Naval Surface Warfare Center (NSWC) are joined and underway with integrated efforts to marry new, fully demonstrated technologies and operational urgencies. Defense funding today cannot sponsor all work that can be mission-justified over the long term because budgets are insufficient to support product maturation within the classical development cycle. However, by rigorous technical filtering and astute engineering of both marketplace capabilities and currently available components, it is possible in a few select cases to compress and, in effect, integrate advanced development (6.3), engineering development (6.4), weapon procurement (WPN), ship construction (SCN), operation and maintenance (O&M,N) budgetary categories when fleet criticalities and technology opportunities can happily meet. In short, 6.3 funds can be applied directly to ''ripe gateways'' so modern technology is inserted into existing troubled or aging systems, sidestepping the lengthy, traditional development cycle and accelerating practical payoffs to recurrent fleet problems. To produce such constructive results has required a remarkable convergence of sponsor prescience and engineering workforce excellence. The paper describes, extensively, the philosophy of approach, transition strategy, polling of fleet needs, technology assessment, and management team requirements. The process for culling and selecting specific candidate tasks for SHARP sponsorship (matching operational need with t

关键词： Naval vessels

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Virtual memory versus file interfaces for large, memory-intensive scientific applications 96

Virtual memory versus file interfaces for large, memory-inte...

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Proceedings of the 1996 ACM/IEEE conference on Supercomputing

作者： Yoonho Park Ridgway Scott Stuart Sechrest High Performance Computing Center University of Houston Houston TX Software Systems Research Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI

ISBN: (纸本)9780897918541

Scientific applications often require some strategy for temporary data storage to do the largest possible simulations. The use of virtual memory for temporary data storage has received criticism because of performance problems. However, modern virtual memory found in recent operating systems such as Cenju-3/DE give application writers control over virtual memory policies. We demonstrate that custom virtual memory policies can dramatically reduce virtual memory overhead and allow applications to run out-of-core efficiently. We also demonstrate that the main advantage of virtual memory, namely programming simplicity, is not lost.

关键词： custom policies

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