Model-based evaluation of reliable distributed and parallel systems is difficult due to the complexity of these systems and the nature of the dependability measures of interest. The complexity creates problems for ana...
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Model-based evaluation of reliable distributed and parallel systems is difficult due to the complexity of these systems and the nature of the dependability measures of interest. The complexity creates problems for analytical model solution techniques, and the fact that reliability and availability measures are based on rare events makes traditional simulation methods inefficient. Importance sampling is a well-known technique for improving the efficiency of rare event simulations. However, finding an importance sampling strategy that works well in general is a difficult problem. The best strategy for importance sampling depends on the characteristics of the system and the dependability measure of interest. This fact motivated the development of an environment for importance sampling that would support the wide variety of model characteristics and interesting measures. The environment is based on stochastic activity networks, and importance sampling strategies are specified using the new concept of the importance sampling governor. The governor supports dynamic importance sampling strategies by allowing the stochastic elements of the model to be redefined based on the evolution of the simulation. The utility of the new environment is demonstrated by evaluating the unreliability of a highly dependable fault-tolerant unit used in the well-known MARS architecture. The model is non-Markovian, with Weibull distributed failure times and uniformly distributed repair times.< >
In numerical simulations of fluid-dynamics problems, solution-adaptive methods have proven to be very powerful. The implementation of the modified Shepard’s interpolation to the structured grids used in CFD is sugges...
In this paper, we present a comparative performance evaluation of hot spot effects on the MIN-based and HR-based shared-memory architectures. Analytical models are described for understanding network differences and f...
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In this paper, we present a comparative performance evaluation of hot spot effects on the MIN-based and HR-based shared-memory architectures. Analytical models are described for understanding network differences and for evaluating hot spot performance on both architectures. The analytical comparisons indicate that HR-based architectures have the potential to handle various contentions caused by hot spots more efficiently than MIN-based architectures. Although there is no analytical and experimental evidence that the tree saturation phenomenon occurs in non-blocking MIN architectures, remote accesses to both hot and cool memory modules are considerably slowed down, and overall performance is significantly degraded. Intensive performance measurements on hot spots have been conducted on the BBN TC2000 (MIN-based) and the KSR1 (HR-based) machines. performance experiments were also conducted on the practical experience of hot spots with respect to synchronization lock and barrier algorithms. The experimental results support the analytical models, and present practical observations and an evaluation of hot spots on the two types of architectures.< >
The authors describe a new portable algorithm for parallel circuit extraction. The algorithm is built as part of the ongoing ProperCAD project: a portable object-oriented parallel environment for CAD applications that...
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The authors describe a new portable algorithm for parallel circuit extraction. The algorithm is built as part of the ongoing ProperCAD project: a portable object-oriented parallel environment for CAD applications that is built on top of the CHARM system. The algorithm, unlike prior approaches like PACE is asynchronous and is based on a coarse-grained dataflow execution model. performance of circuit extraction is presented on four parallel machines: an Encore Multimax, a Sequent Symmetry, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. The extractor runs unchanged on all these machines.< >
An algorithm based on the transduction method and implemented in the ProperCAD environment is described. The parallel ProperSYN algorithm attempts to make the execution time manageably small. The algorithm uses an asy...
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An algorithm based on the transduction method and implemented in the ProperCAD environment is described. The parallel ProperSYN algorithm attempts to make the execution time manageably small. The algorithm uses an asynchronous message driven computing model with no synchronizing barriers, and hence it is scalable to a larger number of processors. Also, the algorithm is portable across a wide variety parallel machines. Experimental results on various parallel machines are presented. The algorithm is built around a well-defined sequential algorithm interface such that there can be benefits from future expansion of the sequential algorithm.< >
Yield analysis for reconfigurable structures is often difficult, due to the defect distribution and irregularity of reconfiguration algorithms. In this paper, the authors give a method to analyze the yield of reconfig...
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Yield analysis for reconfigurable structures is often difficult, due to the defect distribution and irregularity of reconfiguration algorithms. In this paper, the authors give a method to analyze the yield of reconfigurable pipelines for the following model: Given n pipelines with m stages, where each stage of a pipeline is defective with constant probability and spare wires are provided for reconfiguration, the authors calculate the expected percentage of pipelines they can harvest after reconfiguration. By modeling the 'shifting' reconfiguration as weighted chains in a lattice and applying poset theory, they give upper and lower bounds for the harvest rate as a function of m and n.< >
The problems of synchronizing communication and clock distribution to various circuit parts has led to interest in self-timed circuits, particularly in ASIC signal processing designs. Self-timed circuits employ comput...
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The problems of synchronizing communication and clock distribution to various circuit parts has led to interest in self-timed circuits, particularly in ASIC signal processing designs. Self-timed circuits employ computational components which generate completion signals to indicate that their data are available for use by other circuit components. Therefore, other circuit components wait for completion signals rather than clock signals. One of the drawbacks of self-timed circuits is that they are difficult to test because they are asynchronous. This paper is concerned with a class of self-timed systems because each logic components generate its completion signals automatically. This paper studies the behaviour of DCVSL logic in the presence of physical faults. Based on this behaviour, the authors present a switch-level test generation algorithm for DCVSL circuits. Finally, they present a scan approach suitable for self-timed systems.< >
Switch-level simulation is widely used in the design verification process of Very Large Scale Integrated (VLSI) MOS circuits. In this paper, the authors present methods for accelerating switch-level simulation by mapp...
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Switch-level simulation is widely used in the design verification process of Very Large Scale Integrated (VLSI) MOS circuits. In this paper, the authors present methods for accelerating switch-level simulation by mapping it onto general purpose parallel computers. Their target machines are medium-grain multiprocessors (shared memory or message passing machines) and they only consider model parallel computation, where the model of the design to be simulated is partitioned among processors. Efficient strategies are introduced for circuit partitioning as well as the corresponding simulation algorithms. In the authors' approach, they try to minimize the total number of synchronizations between processors, as well as ensure portability and scalability. A preprocessor and simulator were implemented and good performance was obtained for a set of benchmarks. The problem of tight coupling between processors that evaluate a strongly connected component in the circuit in a distributed fashion is highlighted.< >
This article discusses an approach for hierarchical multilevel fault simulation for large systems described at the transistor, gate, and higher levels. The approach reduces the memory requirement of the simulation dra...
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The analysis of fault-tolerant multiprocessor systems that use concurrent error detection (CED) schemes is much more difficult than the analysis of conventional fault-tolerant architectures. Various analytical techniq...
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