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IEEE International Conference on computer-Aided Design

作者： De Ramkumar Banerjee Center for Reliable & High-Perf. Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Department of Electrical & Computer Engineering University of Iowa Iowa IA USA

An algorithm based on the transduction method and implemented in the ProperCAD environment is described. The parallel ProperSYN algorithm attempts to make the execution time manageably small. The algorithm uses an asynchronous message driven computing model with no synchronizing barriers, and hence it is scalable to a larger number of processors. Also, the algorithm is portable across a wide variety parallel machines. Experimental results on various parallel machines are presented. The algorithm is built around a well-defined sequential algorithm interface such that there can be benefits from future expansion of the sequential algorithm.< >

关键词： Design automation Parallel algorithms

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Harvest rate of reconfigurable pipelines

Harvest rate of reconfigurable pipelines

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： Weiping Shi Ming-Feng Chang W. Kent Fuchs Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Department of Computer Science and Information Engineering National Chiao Tung University Taiwan

Yield analysis for reconfigurable structures is often difficult, due to the defect distribution and irregularity of reconfiguration algorithms. In this paper, the authors give a method to analyze the yield of reconfigurable pipelines for the following model: Given n pipelines with m stages, where each stage of a pipeline is defective with constant probability and spare wires are provided for reconfiguration, the authors calculate the expected percentage of pipelines they can harvest after reconfiguration. By modeling the 'shifting' reconfiguration as weighted chains in a lattice and applying poset theory, they give upper and lower bounds for the harvest rate as a function of m and n.< >

关键词： Pipelines Wires Lattices Very large scale integration Switches Algorithm design and analysis Parallel architectures Supercomputers Equations engineering management

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Fault modeling and testing of self-timed circuits

Fault modeling and testing of self-timed circuits

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VLSI Test Symposium

作者： S.S. Guillory D.G. Saab A. Yang Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Department of Electrical Engineering University of Washington Seattle WA USA

The problems of synchronizing communication and clock distribution to various circuit parts has led to interest in self-timed circuits, particularly in ASIC signal processing designs. Self-timed circuits employ computational components which generate completion signals to indicate that their data are available for use by other circuit components. Therefore, other circuit components wait for completion signals rather than clock signals. One of the drawbacks of self-timed circuits is that they are difficult to test because they are asynchronous. This paper is concerned with a class of self-timed systems because each logic components generate its completion signals automatically. This paper studies the behaviour of DCVSL logic in the presence of physical faults. Based on this behaviour, the authors present a switch-level test generation algorithm for DCVSL circuits. Finally, they present a scan approach suitable for self-timed systems.< >

关键词： Circuit testing Circuit faults Automatic testing Clocks Signal generators Synchronization Application specific integrated circuits Signal processing Process design Signal design

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Parallel switch-level simulation for VLSI

Parallel switch-level simulation for VLSI

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European Conference on Design Automation

作者： R.B. Mueller-Thuns D.G. Saab J.A. Abraham Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Computer Engineering Research Center University of Texas Austin Austin TX USA

Switch-level simulation is widely used in the design verification process of Very Large Scale Integrated (VLSI) MOS circuits. In this paper, the authors present methods for accelerating switch-level simulation by mapping it onto general purpose parallel computers. Their target machines are medium-grain multiprocessors (shared memory or message passing machines) and they only consider model parallel computation, where the model of the design to be simulated is partitioned among processors. Efficient strategies are introduced for circuit partitioning as well as the corresponding simulation algorithms. In the authors' approach, they try to minimize the total number of synchronizations between processors, as well as ensure portability and scalability. A preprocessor and simulator were implemented and good performance was obtained for a set of benchmarks. The problem of tight coupling between processors that evaluate a strongly connected component in the circuit in a distributed fashion is highlighted.< >

关键词： Very large scale integration Computational modeling Circuit simulation Concurrent computing Switching circuits Process design Acceleration computer simulation Message passing Partitioning algorithms

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Hierarchical multi-level fault simulation of large systems

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Journal of Electronic Testing 1990年第2期1卷 139-149页

作者： Saab, Daniel G. Mueller-Thuns, Robert B. Blaauw, David Rahmeh, Joseph T. Abraham, Jacob A. Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois at Urbana-Champaign Urbana 61801 IL United States Computer Engineering Research Center University of Texas at Austin Austin 78712 TX United States

This article discusses an approach for hierarchical multilevel fault simulation for large systems described at the transistor, gate, and higher levels. The approach reduces the memory requirement of the simulation drastically, thus allowing the simulation of circuits that are too large to simulate at one flat level on typical engineering workstations. This is achieved by exploiting the regularity and modularity found in a hierarchical circuit description that contains many repeated substructures. The hierarchical setup also allows flexible multilevel simulation: behavioral models can replace subcircuits at any level of the hierarchy for accelerated simulation. The simulation algorithms are at the switch level so that general MOS digital designs with bidirectional signal flow can be handled, and both stuck-at and transistor faults are treated accurately. The approach has been implemented in the hierarchical logic and fault simulation system, CHAMP, that runs under UNIX on SUN-3 and SUN-4 workstations. It has been used successfully for simulating and fault grading a large commercial microprocessor. © 1990 Kluwer Academic Publishers.

关键词： fault simulation multilevel simulation testing VLSI design

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A probabilistic model for the evaluation of fault-tolerant multiprocessor systems using concurrent error detection

A probabilistic model for the evaluation of fault-tolerant m...

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Advanced Signal Processing Algorithms, Architectures, and Implementations 1990

作者： Nair, V.S.S. Abraham, J.A. Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois at Urbana-Champaign UrbanaIL61801 United States Computer Engineering Research Center University of Texas at Austin AustinTX78758 United States

The analysis of fault-tolerant multiprocessor systems that use concurrent error detection (CED) schemes is much more difficult than the analysis of conventional fault-tolerant architectures. Various analytical techniques have been proposed to evaluate CED schemes deterministically. However, these approaches are based on the worst-case assumptions related to the failure of system components. Often, the evaluation results are not good measures for comparing the fault tolerance capabilities of a system. In this paper, we develop a probabilistic approach to evaluate and compare fault-tolerant multiprocessor systems. Various probabilities associated with CED schemes are identified and used in the framework of the matrix-based model which we had proposed previously. Based on these probabilistic matrices, we analytically derive estimates for the fault tolerance capabilities of various systems. © 1990 SPIE. All rights reserved.

关键词： Fault tolerance

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Automatic classification of node types in switch-level descriptions

Automatic classification of node types in switch-level descr...

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： D.T. Blaauw P. Banerjee J.A. Abraham Center for Reliable an High Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Department of Electrical & Computer Engineering University of Texas Austin Austin TX USA

In switch-level simulation, nodes carry a charge on their parasitic capacitance from one evaluation to the next, which gives them a memory quality. A node is classified as temporary if its memory aspect is lost and cannot affect the circuit operation, whereas a node is classified as a memory node if the memory of the node is maintained and can affect the circuit operation. Accurate classification of nodes into temporary and memory nodes increases the performance of compiled simulators and high-level model generators. An approach for reliable automatic classification of nodes in a switch-level description is introduced. Both an exhaustive, exponential-time algorithm and a polynomial-time heuristic are presented. The heuristic was implemented and tested for several large circuits, including a commercial microprocessor. For this processor, the proposed heuristics identified an average of 92% of all nodes as temporary nodes. The heuristic was applied in a high-level model generator and significantly increased its performance.< >

关键词： Circuit simulation Parasitic capacitance Circuit testing Maintenance Polynomials Switching circuits Switched capacitor circuits Joining processes Capacitance measurement Size measurement

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Fault grading of large digital systems

Fault grading of large digital systems

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： D.G. Saab R.B. Mueller-Thuns D. Blaauw J.T. Rahmeh J.A. Abraham Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Computer Engineering Research Center Depatment of Electrical and Computer Engineering University of Texas Austin Austin TX USA

Cost-effective and accurate fault simulation of very large digital designs on engineering workstations is proposed. The hierarchical approach reduces memory requirements drastically by storing the structure of common repeated subcircuits only once. The approach allows flexible multilevel simulation. The simulation algorithms are at the switch-level so that general MOS digital designs with bidirectional signal flow can be handled, and both stuck-at and transistor faults are treated accurately. The fault simulation algorithms have been implemented as a prototype that was used to determine the fault grade of a model of the Motorola 68000 microprocessor on SUN Microsystems workstations.< >

关键词： Digital systems Circuit simulation Circuit faults Computational modeling Switches Circuit testing MOSFETs Logic circuits Adders Workstations

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Design of a scalable parallel switch-level simulator for VLSI

Design of a scalable parallel switch-level simulator for VLS...

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Supercomputing Conference

The problem of mapping a computation-intensive task of irregular structure onto a parallel framework is examined. The application considered is the switch-level logic simulation of digital circuits, a technique that is in wide use for the verification of VLSI designs. The authors focus on medium-grain multiprocessors and only consider model parallel computation, where the model of the design to be simulated is partitioned among processors. They address the issues of portability and scalability and look at specific features of the application that can be exploited. Different ways of mapping the simulation problem onto a parallel framework are presented. A prototype implementation of the algorithms is described.< >

关键词： Very large scale integration Computational modeling Circuit simulation Concurrent computing Switching circuits Logic design Logic circuits Digital circuits Scalability Prototypes

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Computational science — ICCS 2003 1

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丛书名： Lecture Notes in computer science

1000年

作者： Peter M. A. Sloot David Abramson Alexander V. Bogdanov Yuriy E. Gorbachev Jack J. Dongarra Albert Y. Zomaya

ISBN: (数字)9783540448631

ISBN: (纸本)9783540401964

Some of the most challenging problems in science and engineering are being addressed by the integration of computation and science, a research ?eld known as computational science. Computational science plays a vital role in fundamental advances in biology, physics, chemistry, astronomy, and a host of other disciplines. This is through the coordination of computation, data management, access to instrumentation, knowledge synthesis, and the use of new devices. It has an impact on researchers and practitioners in the sciences and beyond. The sheer size of many challenges in computational science dictates the use of supercomputing, parallel and distri- ted processing, grid-based processing, advanced visualization and sophisticated algorithms. At the dawn of the 21st century the series of International Conferences on Computational science (ICCS) was initiated with a ?rst meeting in May 2001 in San Francisco. The success of that meeting motivated the organization of the - cond meeting held in Amsterdam April 21–24, 2002, where over 500 participants pushed the research ?eld further. The International Conference on Computational science 2003 (ICCS 2003) is the follow-up to these earlier conferences. ICCS 2003 is unique, in that it was a single event held at two di?erent sites almost opposite each other on the globe – Melbourne, Australia and St. Petersburg, Russian Federation. The conference ran on the same dates at both locations and all the presented work was published in a single set of proceedings, which you hold in your hands right now.

关键词： Theory of Computation Programming Techniques computer Systems Organization and Communication Networks Mathematics of computing Information Systems and Communication Service computer Imaging, Vision, Pattern Recognition and Graphics

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