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检索条件"机构=High Performance Computing Laboratory Department of Computer Science and Engineering"
1183 条 记 录,以下是1151-1160 订阅
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An environment for importance sampling based on stochastic activity networks
An environment for importance sampling based on stochastic a...
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Reliable Distributed Systems
作者: W.D. Obal W.H. Sanders Department of Electrical and Computer Engineering University of Arizona Tucson Tucson AZ USA Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA
Model-based evaluation of reliable distributed and parallel systems is difficult due to the complexity of these systems and the nature of the dependability measures of interest. The complexity creates problems for ana... 详细信息
来源: 评论
Shepard’s interpolation for solution-adaptive methods
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Journal of Computational Physics 1993年 第1期106卷 52-61页
作者: Shen, Cherng-Yeu Reed, Helen L. Foley, Thomas A. Mechanical and Aerospace Engineering Department Arizona State University Tempe AZ United States Computer Science and Engineering Department Arizona State University Tempe AZ United States National Cemter for High-Performance Computing Taiwan
In numerical simulations of fluid-dynamics problems, solution-adaptive methods have proven to be very powerful. The implementation of the modified Shepard’s interpolation to the structured grids used in CFD is sugges...
来源: 评论
Modeling and measuring hot spots on MIN-based and HR-based shared-memory architectures
Modeling and measuring hot spots on MIN-based and HR-based s...
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International Symposium on Parallel and Distributed Processing (IPDPS)
作者: X. Zhang Y. Yan R. Castaneda High Performance Computing and Software Laboratory University of Texas San Antonio San Antonio TX USA Department of computer science Huazhong University of Science and Technology Wuhan China
In this paper, we present a comparative performance evaluation of hot spot effects on the MIN-based and HR-based shared-memory architectures. Analytical models are described for understanding network differences and f... 详细信息
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A portable parallel algorithm for VLSI circuit extraction
A portable parallel algorithm for VLSI circuit extraction
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International Symposium on Parallel Processing
作者: B. Ramkumar P. Banerjee Department of Electrical & Computer Engineering University of Iowa USA Center for Reliable and High-Perf Computing Coordinated Science Laboratory University of Illinois USA
The authors describe a new portable algorithm for parallel circuit extraction. The algorithm is built as part of the ongoing ProperCAD project: a portable object-oriented parallel environment for CAD applications that... 详细信息
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ProperSYN: A portable parallel algorithm for logic synthesis
ProperSYN: A portable parallel algorithm for logic synthesis
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IEEE International Conference on computer-Aided Design
作者: De Ramkumar Banerjee Center for Reliable & High-Perf. Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Department of Electrical & Computer Engineering University of Iowa Iowa IA USA
An algorithm based on the transduction method and implemented in the ProperCAD environment is described. The parallel ProperSYN algorithm attempts to make the execution time manageably small. The algorithm uses an asy... 详细信息
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Harvest rate of reconfigurable pipelines
Harvest rate of reconfigurable pipelines
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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
作者: Weiping Shi Ming-Feng Chang W. Kent Fuchs Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Department of Computer Science and Information Engineering National Chiao Tung University Taiwan
Yield analysis for reconfigurable structures is often difficult, due to the defect distribution and irregularity of reconfiguration algorithms. In this paper, the authors give a method to analyze the yield of reconfig... 详细信息
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Fault modeling and testing of self-timed circuits
Fault modeling and testing of self-timed circuits
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VLSI Test Symposium
作者: S.S. Guillory D.G. Saab A. Yang Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Department of Electrical Engineering University of Washington Seattle WA USA
The problems of synchronizing communication and clock distribution to various circuit parts has led to interest in self-timed circuits, particularly in ASIC signal processing designs. Self-timed circuits employ comput... 详细信息
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Parallel switch-level simulation for VLSI
Parallel switch-level simulation for VLSI
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European Conference on Design Automation
作者: R.B. Mueller-Thuns D.G. Saab J.A. Abraham Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Computer Engineering Research Center University of Texas Austin Austin TX USA
Switch-level simulation is widely used in the design verification process of Very Large Scale Integrated (VLSI) MOS circuits. In this paper, the authors present methods for accelerating switch-level simulation by mapp... 详细信息
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Hierarchical multi-level fault simulation of large systems
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Journal of Electronic Testing 1990年 第2期1卷 139-149页
作者: Saab, Daniel G. Mueller-Thuns, Robert B. Blaauw, David Rahmeh, Joseph T. Abraham, Jacob A. Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois at Urbana-Champaign Urbana 61801 IL United States Computer Engineering Research Center University of Texas at Austin Austin 78712 TX United States
This article discusses an approach for hierarchical multilevel fault simulation for large systems described at the transistor, gate, and higher levels. The approach reduces the memory requirement of the simulation dra... 详细信息
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A probabilistic model for the evaluation of fault-tolerant multiprocessor systems using concurrent error detection
A probabilistic model for the evaluation of fault-tolerant m...
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Advanced Signal Processing Algorithms, Architectures, and Implementations 1990
作者: Nair, V.S.S. Abraham, J.A. Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois at Urbana-Champaign UrbanaIL61801 United States Computer Engineering Research Center University of Texas at Austin AustinTX78758 United States
The analysis of fault-tolerant multiprocessor systems that use concurrent error detection (CED) schemes is much more difficult than the analysis of conventional fault-tolerant architectures. Various analytical techniq... 详细信息
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