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Reliable Distributed Systems

作者： W.D. Obal W.H. Sanders Department of Electrical and Computer Engineering University of Arizona Tucson Tucson AZ USA Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA

Model-based evaluation of reliable distributed and parallel systems is difficult due to the complexity of these systems and the nature of the dependability measures of interest. The complexity creates problems for analytical model solution techniques, and the fact that reliability and availability measures are based on rare events makes traditional simulation methods inefficient. Importance sampling is a well-known technique for improving the efficiency of rare event simulations. However, finding an importance sampling strategy that works well in general is a difficult problem. The best strategy for importance sampling depends on the characteristics of the system and the dependability measure of interest. This fact motivated the development of an environment for importance sampling that would support the wide variety of model characteristics and interesting measures. The environment is based on stochastic activity networks, and importance sampling strategies are specified using the new concept of the importance sampling governor. The governor supports dynamic importance sampling strategies by allowing the stochastic elements of the model to be redefined based on the evolution of the simulation. The utility of the new environment is demonstrated by evaluating the unreliability of a highly dependable fault-tolerant unit used in the well-known MARS architecture. The model is non-Markovian, with Weibull distributed failure times and uniformly distributed repair times.< >

关键词： Monte Carlo methods Stochastic processes Analytical models Discrete event simulation Availability Sampling methods Stochastic systems computer network reliability computer networks Concurrent computing

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Shepard’s interpolation for solution-adaptive methods

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Journal of Computational Physics 1993年第1期106卷 52-61页

作者： Shen, Cherng-Yeu Reed, Helen L. Foley, Thomas A. Mechanical and Aerospace Engineering Department Arizona State University Tempe AZ United States Computer Science and Engineering Department Arizona State University Tempe AZ United States National Cemter for High-Performance Computing Taiwan

In numerical simulations of fluid-dynamics problems, solution-adaptive methods have proven to be very powerful. The implementation of the modified Shepard’s interpolation to the structured grids used in CFD is suggested and described in this paper, which takes advantage of the logical grid structure. This technique, which is demonstrated to be robust, efficient, smoother, and a more accurate alternative to linear interpolation, is used in the remapping step during the solution-adaption procedure. Applications to the solutions of the incompressible Navier Stokes equations (both 2D and 3D) are included. © 1993 by Academic Press, Inc.

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Modeling and measuring hot spots on MIN-based and HR-based shared-memory architectures

Modeling and measuring hot spots on MIN-based and HR-based s...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： X. Zhang Y. Yan R. Castaneda High Performance Computing and Software Laboratory University of Texas San Antonio San Antonio TX USA Department of computer science Huazhong University of Science and Technology Wuhan China

In this paper, we present a comparative performance evaluation of hot spot effects on the MIN-based and HR-based shared-memory architectures. Analytical models are described for understanding network differences and for evaluating hot spot performance on both architectures. The analytical comparisons indicate that HR-based architectures have the potential to handle various contentions caused by hot spots more efficiently than MIN-based architectures. Although there is no analytical and experimental evidence that the tree saturation phenomenon occurs in non-blocking MIN architectures, remote accesses to both hot and cool memory modules are considerably slowed down, and overall performance is significantly degraded. Intensive performance measurements on hot spots have been conducted on the BBN TC2000 (MIN-based) and the KSR1 (HR-based) machines. performance experiments were also conducted on the practical experience of hot spots with respect to synchronization lock and barrier algorithms. The experimental results support the analytical models, and present practical observations and an evaluation of hot spots on the two types of architectures.< >

关键词： Telecommunication traffic computer architecture high performance computing Software performance Laboratories Degradation Switches computer science Traffic control Analytical models

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A portable parallel algorithm for VLSI circuit extraction

A portable parallel algorithm for VLSI circuit extraction

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International Symposium on Parallel Processing

作者： B. Ramkumar P. Banerjee Department of Electrical & Computer Engineering University of Iowa USA Center for Reliable and High-Perf Computing Coordinated Science Laboratory University of Illinois USA

The authors describe a new portable algorithm for parallel circuit extraction. The algorithm is built as part of the ongoing ProperCAD project: a portable object-oriented parallel environment for CAD applications that is built on top of the CHARM system. The algorithm, unlike prior approaches like PACE is asynchronous and is based on a coarse-grained dataflow execution model. performance of circuit extraction is presented on four parallel machines: an Encore Multimax, a Sequent Symmetry, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. The extractor runs unchanged on all these machines.< >

关键词： Parallel algorithms Very large scale integration Object oriented modeling Concurrent computing Workstations Circuit testing Runtime library Portable computers Application software Parallel machines

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ProperSYN: A portable parallel algorithm for logic synthesis

ProperSYN: A portable parallel algorithm for logic synthesis

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IEEE International Conference on computer-Aided Design

作者： De Ramkumar Banerjee Center for Reliable & High-Perf. Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Department of Electrical & Computer Engineering University of Iowa Iowa IA USA

An algorithm based on the transduction method and implemented in the ProperCAD environment is described. The parallel ProperSYN algorithm attempts to make the execution time manageably small. The algorithm uses an asynchronous message driven computing model with no synchronizing barriers, and hence it is scalable to a larger number of processors. Also, the algorithm is portable across a wide variety parallel machines. Experimental results on various parallel machines are presented. The algorithm is built around a well-defined sequential algorithm interface such that there can be benefits from future expansion of the sequential algorithm.< >

关键词： Design automation Parallel algorithms

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Harvest rate of reconfigurable pipelines

Harvest rate of reconfigurable pipelines

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： Weiping Shi Ming-Feng Chang W. Kent Fuchs Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Department of Computer Science and Information Engineering National Chiao Tung University Taiwan

Yield analysis for reconfigurable structures is often difficult, due to the defect distribution and irregularity of reconfiguration algorithms. In this paper, the authors give a method to analyze the yield of reconfigurable pipelines for the following model: Given n pipelines with m stages, where each stage of a pipeline is defective with constant probability and spare wires are provided for reconfiguration, the authors calculate the expected percentage of pipelines they can harvest after reconfiguration. By modeling the 'shifting' reconfiguration as weighted chains in a lattice and applying poset theory, they give upper and lower bounds for the harvest rate as a function of m and n.< >

关键词： Pipelines Wires Lattices Very large scale integration Switches Algorithm design and analysis Parallel architectures Supercomputers Equations engineering management

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Fault modeling and testing of self-timed circuits

Fault modeling and testing of self-timed circuits

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VLSI Test Symposium

作者： S.S. Guillory D.G. Saab A. Yang Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Department of Electrical Engineering University of Washington Seattle WA USA

The problems of synchronizing communication and clock distribution to various circuit parts has led to interest in self-timed circuits, particularly in ASIC signal processing designs. Self-timed circuits employ computational components which generate completion signals to indicate that their data are available for use by other circuit components. Therefore, other circuit components wait for completion signals rather than clock signals. One of the drawbacks of self-timed circuits is that they are difficult to test because they are asynchronous. This paper is concerned with a class of self-timed systems because each logic components generate its completion signals automatically. This paper studies the behaviour of DCVSL logic in the presence of physical faults. Based on this behaviour, the authors present a switch-level test generation algorithm for DCVSL circuits. Finally, they present a scan approach suitable for self-timed systems.< >

关键词： Circuit testing Circuit faults Automatic testing Clocks Signal generators Synchronization Application specific integrated circuits Signal processing Process design Signal design

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Parallel switch-level simulation for VLSI

Parallel switch-level simulation for VLSI

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European Conference on Design Automation

作者： R.B. Mueller-Thuns D.G. Saab J.A. Abraham Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Computer Engineering Research Center University of Texas Austin Austin TX USA

Switch-level simulation is widely used in the design verification process of Very Large Scale Integrated (VLSI) MOS circuits. In this paper, the authors present methods for accelerating switch-level simulation by mapping it onto general purpose parallel computers. Their target machines are medium-grain multiprocessors (shared memory or message passing machines) and they only consider model parallel computation, where the model of the design to be simulated is partitioned among processors. Efficient strategies are introduced for circuit partitioning as well as the corresponding simulation algorithms. In the authors' approach, they try to minimize the total number of synchronizations between processors, as well as ensure portability and scalability. A preprocessor and simulator were implemented and good performance was obtained for a set of benchmarks. The problem of tight coupling between processors that evaluate a strongly connected component in the circuit in a distributed fashion is highlighted.< >

关键词： Very large scale integration Computational modeling Circuit simulation Concurrent computing Switching circuits Process design Acceleration computer simulation Message passing Partitioning algorithms

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Hierarchical multi-level fault simulation of large systems

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Journal of Electronic Testing 1990年第2期1卷 139-149页

作者： Saab, Daniel G. Mueller-Thuns, Robert B. Blaauw, David Rahmeh, Joseph T. Abraham, Jacob A. Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois at Urbana-Champaign Urbana 61801 IL United States Computer Engineering Research Center University of Texas at Austin Austin 78712 TX United States

This article discusses an approach for hierarchical multilevel fault simulation for large systems described at the transistor, gate, and higher levels. The approach reduces the memory requirement of the simulation drastically, thus allowing the simulation of circuits that are too large to simulate at one flat level on typical engineering workstations. This is achieved by exploiting the regularity and modularity found in a hierarchical circuit description that contains many repeated substructures. The hierarchical setup also allows flexible multilevel simulation: behavioral models can replace subcircuits at any level of the hierarchy for accelerated simulation. The simulation algorithms are at the switch level so that general MOS digital designs with bidirectional signal flow can be handled, and both stuck-at and transistor faults are treated accurately. The approach has been implemented in the hierarchical logic and fault simulation system, CHAMP, that runs under UNIX on SUN-3 and SUN-4 workstations. It has been used successfully for simulating and fault grading a large commercial microprocessor. © 1990 Kluwer Academic Publishers.

关键词： fault simulation multilevel simulation testing VLSI design

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A probabilistic model for the evaluation of fault-tolerant multiprocessor systems using concurrent error detection

A probabilistic model for the evaluation of fault-tolerant m...

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Advanced Signal Processing Algorithms, Architectures, and Implementations 1990

作者： Nair, V.S.S. Abraham, J.A. Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois at Urbana-Champaign UrbanaIL61801 United States Computer Engineering Research Center University of Texas at Austin AustinTX78758 United States

The analysis of fault-tolerant multiprocessor systems that use concurrent error detection (CED) schemes is much more difficult than the analysis of conventional fault-tolerant architectures. Various analytical techniques have been proposed to evaluate CED schemes deterministically. However, these approaches are based on the worst-case assumptions related to the failure of system components. Often, the evaluation results are not good measures for comparing the fault tolerance capabilities of a system. In this paper, we develop a probabilistic approach to evaluate and compare fault-tolerant multiprocessor systems. Various probabilities associated with CED schemes are identified and used in the framework of the matrix-based model which we had proposed previously. Based on these probabilistic matrices, we analytically derive estimates for the fault tolerance capabilities of various systems. © 1990 SPIE. All rights reserved.

关键词： Fault tolerance

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