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检索条件"机构=High Performance Computing Laboratory Department of Computer Science and Engineering"

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The Library for Hadoop Deflate Compression Based on FPGA Accelerator with Load Balance 20

The Library for Hadoop Deflate Compression Based on FPGA Acc...

引用

20th International Conference on Parallel and Distributed computing, Applications and Technologies, PDCAT 2019

作者： Du, Haixin Zhang, Jiankui Sha, Shihao Ye, Cai Luo, Qiuming College of Computer Science and Software Engineering Shenzhen University NHPCC/Guangdong Key Laboratory of Popular HPC Guangdong Province Engineering Center of China-made High Performance Data Computing System Shenzhen China

ISBN: (纸本)9781728126166

Hadoop application will produce lots of intermediate results in the map/reduce process that requires disk I/O and network transmission. By compressing the large-scale data of intermediate result, it will greatly improve disk access efficiently and reduce program run time. Hardware-accelerated solutions have become more desirable. This paper design a multi-FPGA compression accelerator on the Hadoop platform, and the system performance analysis compared with a software-only solution that mainly uses CPU to processing. The testing programs are zpipe, TestDFSIO and Terasort. In contrast with the software-only solution. The max speedup of zpipe is 6.55X (single FPGA) and 10.24X (dual FPGA), the max speedup of TestDFSIO is 6.28X (single FPGA) and 6.28X (dual FPGA), and the max speedup of Terasort application is up to 3.25X(single FPGA) and 3.35X(dual FPGA). © 2019 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A holistic stream partitioning algorithm for distributed stream processing systems 20

A holistic stream partitioning algorithm for distributed str...

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20th International Conference on Parallel and Distributed computing, Applications and Technologies, PDCAT 2019

作者： Li, Kejian Liu, Gang Lu, Minhua Guangdong Province Key Laboratory of Popular High Performance Computers Guangdong Province Engineering Center of China-made High Performance Data Computing System College of Computer Science and Software Engineering Shenzhen University Shenzhen518060 China School of Biomedical Engineering Shenzhen University Shenzhen518060 China

ISBN: (纸本)9781728126166

The performances of modern distributed stream processing systems are critically affected by the distribution of the load across workers. Skewed data streams in real world are very common and pose a great challenge to these systems, especially for stateful applications. Key splitting, which allows a single key to be routed to multiple workers, is a great idea to achieve good balance of load in the cluster. However, it comes with the cost of increased memory consumption and computation overhead as well as network communication. In this paper, we present a new definition of metric to model the cost of key splitting for intra-operator parallelism in stream processing systems and provide a novel perspective to reduce replication factor while keeping both overall load imbalance and processing latency low. Similar to previous work, our approach treats the head and the tail of the distribution differently in order to reduce memory requirements. For the head, it uses our proposed notion of regional load imbalance to decide dynamically whether to make one more worker responsible for the heavy hitter or not. For the tail, it simply uses hash partitioning to keep the size of the routing table for the head as small as possible. Extensive experimental evaluation demonstrates that our approach provides superior performance compared to the state-of-the-art partitioning algorithms in terms of load imbalance, replication factor and latency over different levels of skewed stream distributions. © 2019 IEEE.

关键词： Distributed parameter control systems

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Rapid prototyping techniques for fuzzy controllers 5th

Rapid prototyping techniques for fuzzy controllers

引用

5th Asian computing science Conference on Advances in computing science, ASIAN 1999

作者： Chantrapornchai, Chantana Tongsima, Sissades Sha, Edwin Silpakorn University Nakorn Pathom7300 Thailand National Electronics and Computer Technology Center High Performance Computing Laboratory Bangkok10400 Thailand Department of Computer Science and Engineering University of Notre Dame Notre DameIN46556 United States

ISBN: (纸本)354066856X

In this paper, a new framework for rapid system design and implementation for fuzzy systems is proposed. The given system specification is separated into two components: A conceptual specification and a parameter specification. The conceptual specification defines the system core, which is rarely changed during the system adjustment and may be implemented in hardware at an early stage of the design process. The parameter specification defines parameters that are often changed and are implemented in software for easy adjustment. Such a partitioning ap- proach integrates both hardware and software capability. The presented methodology gives a rapid prototyping and efficient system tuning process which, therefore, can reduce the development cycle time and increase flexibility when designing fuzzy systems. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Rapid prototyping

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Parallel erasure coding: Exploring task parallelism in erasure coding for enhanced bandwidth and energy efficiency 11

Parallel erasure coding: Exploring task parallelism in erasu...

引用

11th IEEE International Conference on Networking Architecture and Storage, NAS 2016

作者： Chen, Hsing-Bung Fu, Song High Performance Computing-Design Group Los Alamos National Laboratory Los AlamosNM87545 United States Department of Computer Science and Engineering University of North Texas DentonTX76203 United States

ISBN: (纸本)9781509033157

Very large data sets within the range of megabytes to terabytes generated daily from checkpoint-and- restart processes are seen in today's scientific simulations. Reliability and durability are two important factors to build an archive storage system. Erasure code based object storage systems are becoming popular choices for archive storage systems due to cost-effective storage space saving schemes and higher fault-resilience capabilities. Both erasure code encoding and decoding procedures involve heavy array, matrix, and table-lookup compute intensive operations. Current solutions of the erasure coding process are based on single process approach which is not capable of processing very large data sets efficient and effectively. In this paper, we address the bottleneck problem of single process erasure encoding by leveraging task parallelism offered by multi-core computers. We add parallel processing capability to the erasure coding process. More specifically, we develop a parallel erasure coding software, called parEC. It explores the MPI run time parallel I/O environment and integrates data placement process for distributing encoded data blocks to destination storage devices. We evaluate the performance of parEC in terms of both encoding throughput and energy efficiency. We also compare the performance of two task scheduling algorithms for parEC. Our experimental results show parEC can significantly reduce the encoding time (i.e., by 74.06%-96.86%) and energy consumption (i.e., by 73.57%-96.86%), and Demand-based Workload Assignment (DBWA) algorithm can a high system utilization (i.e., 95.23%). © 2016 IEEE.

关键词： Energy efficiency

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CoChain: high Concurrency Blockchain Sharding via Consensus on Consensus 42

CoChain: High Concurrency Blockchain Sharding via Consensus ...

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42nd IEEE International Conference on computer Communications, INFOCOM 2023

作者： Li, Mingzhe Lin, You Zhang, Jin Wang, Wei Southern University of Science and Technology Guangdong Provincial Key Laboratory of Brain-Inspired Intelligent Computation Research Institute of Trustworthy Autonomous Systems Computer Science and Engineering Department China Hong Kong University of Science and Technology Computer Science and Engineering Department Hong Kong Institute of High Performance Computing and Agency for Science Technology and Research Singapore

ISBN: (纸本)9798350334142

Sharding is an effective technique to improve the scalability of blockchain. It splits nodes into multiple groups so that they can process transactions in parallel. To achieve higher parallelism and concurrency at large scales, it is desirable to maintain a large number of small shards. However, simply configuring small shards easily results in a higher fraction of malicious nodes inside shards, causing shard corruption and compromising system security. Existing sharding techniques hence demand large shards, at the expense of limited concurrency. To address this limitation, we propose CoChain: a blockchain sharding system that can securely configure small shards for enhanced concurrency. CoChain allows some shards to be corrupted. For security, each shard is monitored by multiple other shards. The latter reach a cross-shard Consensus on the Consensus results of their monitored shard. Once a corrupted shard is found, its subsequent consensus will be taken over by another shard, hence recovering the system. Via Consensus on Consensus, CoChain allows the existence of shards with more fraction of malicious nodes ( © 2023 IEEE.

关键词： Blockchain

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A modified integer-coding genetic algorithm for job shop scheduling problem

A modified integer-coding genetic algorithm for job shop sch...

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8th Pacific Rim International Conference on Artificial Intelligence, PRICAI 2004

作者： Wu, Chunguo Xiang, Wei Liang, Yanchun Lee, Heow Pueh Zhou, Chunguang College of Computer Science and Technology Jilin University Key Laboratory of Symbol Computation and Knowledge Engineering of the Ministry of Education Changchun130012 China Institute of High Performance Computing Singapore117528 Singapore

ISBN: (纸本)3540228179

An operation template is proposed in this paper for describing the mapping between operations and a subset of natural numbers. With such operation template, a job shop scheduling problem (JSSP) can be transformed into a traveling salesman problem (TSP), hence the integer-coding genetic algorithm for TSP can be easily applied and modified. A decoding strategy, called virtual job shop, is proposed to evaluate the fitness of the individual in GA population. The integration of the operation template and virtual job shop makes the existing integer-coding GA possible for solving an extension of a classical job shop scheduling problem. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Traveling salesman problem

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PancakeFS: A Write Efficiently and Read Optimized Filesystem 4

PancakeFS: A Write Efficiently and Read Optimized Filesystem

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4th International Conference on Consumer Electronics and computer engineering, ICCECE 2024

作者： Wang, Yongkang Liu, Yang Chen, Zhiguang School of Computer Science and Engineering Sun Yat-sen University Guangzhou China Institute for Quantum Information College of Computer National University of Defense Technology State Key Laboratory of High-Performance Computing Changsha China

ISBN: (纸本)9798350384062

With the development of emerging technologies such as cloud computing and large AI models (such as LLM), many applications have placed higher demands on the intensive read and write processing of massive data. Addressing the limitations of traditional file systems, we propose PancakeFS, an LSM-Tree-based file system. Leveraging the write-friendly characteristics of LSM-Tree, PancakeFS exhibits efficient write performance. We improve read performance through the design of an inode allocation algorithm based on subtree partitioning and optimization of the disk layout for hot data reconstruction. Our experimental results demonstrate that PancakeFS outperforms Ext4 and TableFS in terms of both read and write performance. © 2024 IEEE.

关键词： Data handling

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Submesh allocation in heterogeneous chip multiprocessors

Submesh allocation in heterogeneous chip multiprocessors

引用

International Conference on Machine Learning and Cybernetics

作者： Zuo, Qi Qiu, Jing High Performance Embedded Computing Library School of Computer Science and Technology Beijing Institute of Technology Beijing 100081 China Department of information science and engineering Hebei University of Science and Technology Shijiazhuang 050018 China

ISBN: (纸本)9781424465262

Lots of submesh allocation strategies are devised in mesh connected computers. In chip multiprocessors connected by network on chip, submesh allocation is also used to allocate processors. Existing research mainly focuses on fragmentation, system performance and algorithmic complexity. The processors are assumed to be homogeneous, and the representation of them only reflects the state of processors usage, free or allocated. However, heterogeneous cores have been widely adopted in modern chip multiprocessors to better support the different computation needs. Therefore, the submesh allocation should be re-designed to reflect the difference between cores in heterogeneous chip multiprocessors. In this paper, a simple submesh allocation strategy based on processor array is presented. The strategy represents the heterogeneous processors by computing power array and usage bitmap. The jobs are represented by needed computing power array. A constrained first fit algorithm is devised to map jobs to the chip multiprocessors. © 2010 IEEE.

关键词： computing power

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Location-aware routing for delay tolerant networks

Location-aware routing for delay tolerant networks

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作者： Tian, Ye Li, Jiang Anhui Province Key Laboratory on High Performance Computing School of Computer Science and Technology University of Science and Technology of China Hefei Anhui 230027 China Department of Systems and Computer Science Howard University Washington DC 20059 United States

ISBN: (纸本)9780984589333

In this paper, we sought to understand the reasons causing failures and delays of message delivery in Delay Tolerant Networks (DTN), and to use this understanding for improving the network. By studying two real-world datasets, we found that node isolation is prevalent, which largely accounts for the inefficiencies in DTN's message delivery. In addition, by analyzing nodes' contact-location relationship, we found that individual and system-wide key locations exist and their existence suggests potential improvements. Motivated by our observations, we designed a location aware routing scheme for DTN networks. With simulation-based experiments, we compared our proposal with other representative DTN routing schemes, and showed that with the awareness of the location information, our solution can deliver more messages within shorter delays, therefore improves the network intensively.

关键词： Delay tolerant networks

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A review on memristive stateful logic

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2013 3rd International Symposium on Chemical engineering and Material Properties, ISCEMP 2013

作者： Fang, Xu Dong Tang, Yu Hua Wu, Jun Jie State Key Laboratory of High Performance Computing School of Computer National University of Defense Technology Changsha 410073 China Department of Computer Science and Technology School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9783037858363

With the realization of physical memristors, using memristors to perform stateful logic operations has been demonstrated feasible. In such operations, memristors simultaneously serve as latches and logic gates, thus enabling the in-situ computing which may open a new computing paradigm for computer architecture. In this paper, we first analyze two types of typical memristive stateful logic gates to reveal the working mechanism of the stateful logic, and then review the recent researches on the memristive stateful logic, and finally discuss the pros and cons of the stateful logic. We reach the conclusion that the stateful logic promises a novel computing paradigm which may revolutionize the conventional computer architecture, while its development is currently subjected to the state drift problem and is constrained by the lack of a general design methodology and physically verification. © (2013) Trans Tech Publications, Switzerland.

关键词： Memristors

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