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International Conference on Machine Learning and Cybernetics (ICMLC)

作者： Qi Zuo Jing Qiu High Performance Embedded Computing Library School of Computer Science and Technology Beijing Institute of Technology Beijing China Department of information science and engineering Hebei University of Science and Technology Shijiazhuang China

Lots of submesh allocation strategies are devised in mesh connected computers. In chip multiprocessors connected by network on chip, submesh allocation is also used to allocate processors. Existing research mainly focuses on fragmentation, system performance and algorithmic complexity. The processors are assumed to be homogeneous, and the representation of them only reflects the state of processors usage, free or allocated. However, heterogeneous cores have been widely adopted in modern chip multiprocessors to better support the different computation needs. Therefore, the submesh allocation should be re-designed to reflect the difference between cores in heterogeneous chip multiprocessors. In this paper, a simple submesh allocation strategy based on processor array is presented. The strategy represents the heterogeneous processors by computing power array and usage bitmap. The jobs are represented by needed computing power array. A constrained first fit algorithm is devised to map jobs to the chip multiprocessors.

关键词： Resource management Arrays computers Algorithm design and analysis Instruction sets Machine learning

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Towards Garbage Collection Mechanism for RTSJ-Oriented Embedded Java Processor

Towards Garbage Collection Mechanism for RTSJ-Oriented Embed...

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International Conference on computer and Information Technology (CIT)

作者： Guang Hu Zhilei Chai Wenke Zhao Shiliang Tu Department of Computer Science Department of Computer Science and Engineering Fudan University Shanghai China Center of Intelligent and High Performance Computing School of Information Technology Jiangnan University Wuxi China Siemens Corporate Technology Beijing China Department of Computer Science and Engineering Fudan University Shanghai China

Currently, Java has been gradually applied in embedded real-time area with the improvement by the Real-Time Specification for Java (RTSJ). Accordingly, a hardware Java execution engine for embedded real-time applications, JPOR-32 (32-bit Java Processor Optimized for RTSJ), is designed. Taking JPOR-32 for an example, this paper presents the garbage collection mechanism for RTSJ-oriented embedded processor in detail. JPOR-32 provides effective architectural support for garbage collection. And the object reference format of JPOR-32 provides supports for objects tracing and heap scanning. The support for write barrier of real-time concurrent GC is also performed. Moreover, JPOR-32 provides optimized instruction level support for garbage collection. In addition, different garbage collection algorithms are compared on the base of the resource-constrained feature and the real-time requirement of the processor, and the hybrid garbage collectors are suggested.

关键词： Java Real time systems Resource management Registers Memory management Loading Head

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A Network Management System Based on DPI

A Network Management System Based on DPI

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International Conference on Network-Based Information Systems (NBIS)

作者： Chu-Sing Yang Ming-Yi Liao Mon-Yen Luo Shin-Min Wang C. Eugene Yeh Institute of Computer and Communication Engineering Department of Electrical Engineering National Cheng Kung University Taiwan Department of Computer Science and Information Engineering National Kaohsiung University of Applied Sciences Kaohsiung Taiwan National Center of High-Performance Computing Taiwan

More and more network applications have appeared in recent years. Government, university, industry and individual Internet users and network services need more bandwidth and various network applications. Many new network protocols are proposed so that it is now becoming harder to manage the network. In the conditional network, every network protocol uses the fixed port, the so-called well-known port number. In the past, it was easy to classify and manage the network traffic because we could identify the network service by the port number. However, new types of network applications do not use fixed port number. The method of traffic classification with fixed port number is inadequate. In recent years, the DPI (Deep Packet Inspection) is used to classify the traffic. This study deploys a NMS (network management system) based on DPI and SNMP. The NMS controls the network devices and services according to the traffic classification of DPIS (DPI server). The platform of DPIS is implemented on the Netfilter framework in Linux kernel.

关键词： Linux Servers Kernel Switches Protocols Inspection Sockets

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Location-aware routing for Delay Tolerant Networks

Location-aware routing for Delay Tolerant Networks

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International Conference on Communications and Networking in China (CHINACOM)

作者： Ye Tian Jiang Li Anhui Province Key Laboratory on High Performance Computing School of Computer Science and Technology University of Science and Technology Hefei Anhui China Department of Systems and Computer Science Howard University College of Medicine Washington D.C. DC USA

In this paper, we sought to understand the reasons causing failures and delays of message delivery in Delay Tolerant Networks (DTN), and to use this understanding for improving the network. By studying two real-world datasets, we found that node isolation is prevalent, which largely accounts for the inefficiencies in DTN's message delivery. In addition, by analyzing nodes' contact-location relationship, we found that individual and system-wide key locations exist and their existence suggests potential improvements. Motivated by our observations, we designed a location aware routing scheme for DTN networks. With simulation-based experiments, we compared our proposal with other representative DTN routing schemes, and showed that with the awareness of the location information, our solution can deliver more messages within shorter delays, therefore improves the network intensively.

关键词： Routing Delay Ad hoc networks Indexes USA Councils Histograms

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Ontology-based intelligent system for malware behavioral analysis

Ontology-based intelligent system for malware behavioral ana...

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IEEE International Conference on Fuzzy Systems (FUZZ-IEEE)

作者： Hsien-Der Huang Tsung-Yen Chuang Yi-Lang Tsai Chang-Shing Lee National Applied Research Laboratories National Center for High Performance Computing Tainan Taiwan Department of Information and Learning Technology National University of Tainan Tainan Taiwan Department of Computer Science and Information Engineering National University of Tainan Tainan Taiwan

This paper proposes an ontology-based intelligent system for malware behavioral analysis. The design background and structure of the Taiwan Malware Analysis Net (TWMAN) are presented to analyze the malware behavior. The TWMAN is composed of the malware behavioral analysis agent and the ontology agent. All of the essential information of the TWMAN, including the malware behavioral ontology, which is store in an ontology repository. The malware behavioral analysis agent collects the malware behavioral information to build malware behavioral ontology and malware behavioral rules. The results from the system logs show that the TWMAN can work effectively based on the malware behavioral analysis to protect the computers from the attack of computer viruses and Trojans.

关键词： Ontologies Internet Analytical models Malware

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Stretchable silicon electronics and their integration with rubber, plastic, paper, vinyl, leather and fabric substrates

Stretchable silicon electronics and their integration with r...

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作者： Kim, Dae-Hyeong Kim, Yun-Soung Liu, Zhuangjian Song, Jizhou Kim, Hoon-Sik Huang, Yonggang Y. Rogers, John A. Departments of Materials Science and Engineering Frederick Seitz Materials Research Laboratory Beckman Institute 1304 West Green Street Urbana IL 61801 United States Institute of High Performance Computing 1 Science Park Road #01-01 The Capricorn Singapore Science Park 11 117528 Singapore Department of Mechanical and Aerospace Engineering University of Miami Coral Gables FL 33146 United States Departments of Civil and Environmental Engineering and Mechanical Engineering Northwestern University Evanston IL 60208 United States Departments of Chemistry Mechanical Engineering Electrical and Computer Engineering University of Illinois at Urbana-Champaign 1304 West Green Street Urbana IL 61801 United States

ISBN: (纸本)9781617387555

Electronic systems that offer elastic mechanical responses to high strain deformations are of growing interest, due to their ability to enable new electrical, optical and biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This paper describes materials and mechanical design strategies for classes of electronic circuits that offer extremely high flexibility and stretchability over large area, enabling them to accommodate even demanding deformation modes, such as twisting and linear stretching to 'rubber-band' levels of strain over 100%. The use of printed single crystalline silicon nanomaterials for the semiconductor provides performance in flexible and stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators and differential amplifiers, suggest a valuable route to high performance stretchable electronics that can be integrated with nearly arbitrary substrates. We show examples ranging from plastic and rubber, to vinyl, leather and paper, with capability for large area coverage. © 2010 Materials Research Society.

关键词： CMOS integrated circuits

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Synchronizing the Timestamps of Concurrent Events in Traces of Hybrid MPI/OpenMP Applications

Synchronizing the Timestamps of Concurrent Events in Traces ...

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IEEE International Conference on Cluster computing

作者： Daniel Becker Markus Geimer Rolf Rabenseifner Felix Wolf Department of Computer Science RWTH Aachen University Aachen Germany German Research School for Simulation Sciences Laboratory for Parallel Programming Aachen Germany Forschungszentrum Jülich Jülich Supercomputing Centre Jülich Germany University of Stuttgart High Performance Computing-Center Stuttgart Germany

Event traces are helpful in understanding the performance behavior of parallel applications since they allow the in-depth analysis of communication and synchronization patterns. However, the absence of synchronized clocks on most cluster systems may render the analysis ineffective because inaccurate relative event timings may misrepresent the logical event order and lead to errors when quantifying the impact of certain behaviors or confuse the users of time-line visualization tools by showing messages flowing backward in time. In our earlier work, we have developed a scalable algorithm that eliminates inconsistent inter-process timings postmortem in traces of pure MPI applications. Since hybrid programming, the combination of MPI and OpenMP in a single application, is becoming more popular on clusters in response to rising numbers of cores per chip and widening shared-memory nodes, we present an extended version of the algorithm that in addition to message-passing event semantics also preserves and restores shared-memory event semantics.

关键词： Clocks Message systems Semantics Synchronization Algorithm design and analysis Interpolation

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Integrated research of parallel computing:Status and future

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Chinese science Bulletin 2009年第11期54卷 1845-1853页

作者： CHEN GuoLiang SUN GuangZhong XU Yun LONG Bai Department of Computer Science and Technology University of Science and Technology of China National High PerformanceComputing Center Anhui Key Laboratory of High Performance Computing Hefei 230027 China

In the past twenty years, the research group in University of science and Technology of China has de-veloped an integrated research method for parallel computing, which is a combination of "Architecture-Algorithm-Programming-Application" . This method is also called the ecological environment of parallel computing research. In this paper, we survey the current status of integrated research method for par-allel computing and by combining the impact of multi-core systems, cloud computing and personal high performance computer, we present our outlook on the future development of parallel computing.

关键词：并行计算综合研究方法高性能计算机科学技术生态环境核系统编程算法

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Using a performance-based skeleton to implement divisible load applications on grid computing environments

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Journal of Information science and engineering 2009年第1期25卷 59-81页

作者： Shih, Wen-Chung Yang, Chao-Tung Tseng, Shian-Shyong Department of Information Science and Applications Asia University Taichung 413 Taiwan High-Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung 407 Taiwan Department of Computer Science National Chiao Tung University Hsinchu 300 Taiwan

Applications with divisible loads have such a rich source of parallelism that their parallelization can significantly reduce their total completion time on grid computing environments. However, it is a challenge for grid users, probably scientists and engineers, to develop their applications which can exploit the computing power of the grid. We propose a performance-based skeleton algorithm for implementing divisible load applications on grids. Following this skeleton, novice grid programmers can easily develop a high performance grid application. To examine the performance of programs developed by this approach, we apply this skeleton to implement three kinds of applications and conduct experiments on our grid test-bed. Experimental results show that programs implemented by this approach run more rapidly than those using conventional scheduling schemes.

关键词： Grid computing

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Using unified parallel C to parallelize the FDTD method of computational electrodynamics

Using unified parallel C to parallelize the FDTD method of c...

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2009 IEEE 13th International Multitopic Conference, INMIC 2009

作者： Hussain, A. Shafi, A. Raza, J. Center for High Performance Scientific Computing Department of Computing NUST School of Electrical Engineering and Computer Science Pakistan

ISBN: (纸本)9781424448722

This paper discusses a parallel implementation of the Finite-Difference Time-Domain (FDTD) method using Unified Parallel C (UPC). UPC is an extension of ANSI C - primarily designed for programming distributed memory parallel hardware. The FDTD method is a powerful and widely used numerical technique in computational electromagnetics community. It is a resource - CPU cycles and memory - hungry technique. Consequently, a parallel implementation is highly desirable to decrease time-to-solution and be able to study larger problems with limited resources. To the best of our knowledge, this is the first attempt to exploit UPC to parallelize the FDTD method. We evaluate the performance of our implementation on a cluster of four SunFire v890 compute nodes-each equipped with 16 processing cores - and report impressive speedups. ©2009 IEEE.

关键词： Finite difference time domain method

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