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Mediterranean Conference on Embedded Computing (MECO)

作者： Chen Liu Florian Kelber Bernhard Vogginger Christian Mayr Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits Technische Universität Dresden Dresden Germany

ISBN: (数字)9798350387568

ISBN: (纸本)9798350387575

In radar target detection, Constant False Alarm Rate is a commonly employed detector known for its simplicity and effectiveness. Its sliding-window detection mechanism possesses computational similarity to convolutional operations in machine learning. With the increasing emergence of AI-enhanced radar processing algorithms, systems at the edge tend to be equipped with machine learning accelerators to expedite matrix multiplications and convolutions. This paper introduces a heuristic algorithm that equivalently transforms Cell-Averaging Constant False Alarm Rate (CA-CFAR) to a convolutional operation coupled with nonlinearity. Comparative experiments of the transformed CA-CFAR utilizing machine learning accelerators against the classical CA-CFAR executed on ARM cores demonstrate that our proposed method significantly reduces the processing latency by 35 to 47 times and saves energy by 30 to 40 times. This advancement brings substantial promise for facilitating real-time high-resolution radar target detection without dedicated CFAR accelerators.

关键词： Program processors Machine learning algorithms Radar detection Radar Object detection Machine learning Transforms

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A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI 5

A Low-Power Hardware Accelerator of MFCC Extraction for Keyw...

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5th IEEE International Conference on Artificial Intelligence circuits and systems, AICAS 2023

作者： Guo, Liyuan Jobst, Matthias Partzsch, Johannes Scholze, Stefan Dixius, Andreas Lohrmann, Matthias Zeinolabedin, Seyed Mohammad Ali Mayr, Christian Technische Universität Chair of Highly-Parallel VLSI-Systems and Neuro-Microelectronics Circuits Dresden Germany Dresden Germany

ISBN: (纸本)9798350332674

With the development of artificial intelligence, the real-time feature extraction of acoustic signals is required in a wide variety of applications, such as keyword spotting and speech recognition. Feature extraction based on Mel-frequency cepstral coefficients (MFCCs) is one of the most significant methods thereinto. A software implementation of the MFCC extraction results in relatively high power consumption and computational time limitation, often making it unsuitable for tiny battery powered devices. Therefore, an on-chip accelerator of MFCC extraction is of interest in cutting-edge scenarios. This paper presents a fixed-point low-power hardware accelerator of MFCC feature extraction implemented in 22nm FDSOI technology. It consumes an average power of 2.78μW for 1024-sample frame at a clock frequency of 1MHz. For keyword spotting, the quantized accelerator achieves an average accuracy of around 96% working along with different classification networks. © 2023 IEEE.

关键词： Feature extraction

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Various Distance Metrics Evaluation on Neural Spike Classification

Various Distance Metrics Evaluation on Neural Spike Classifi...

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2022 IEEE Biomedical circuits and systems Conference, BioCAS 2022

作者： Guo, Shengpeng Guo, Liyuan Zeinolabedin, Seyed Mohammad Ali Mayr, Christian Technische Universität Dresden Chair of Highly-Parallel VLSI-Systems Neuro-Microelectronics Circuits Dresden Germany

ISBN: (数字)9781665469173

ISBN: (纸本)9781665469173

State-of-the-art neuroscience applications require the classification of action potential activities (or spikes) recorded by multi-channel electrodes, named spike sorting. A typical spike sorting algorithm involves three parts: detection, feature extraction, and training/classification. Training/classification stages are mainly based on distance-based algorithms like K-means. For the classification in particular, the accuracy depends highly on the distance metric performance. In this paper, we analyze several distance metrics to classify various datasets with different noise levels using the F1-score. This includes Manhattan, Euclidean and, Mahalanobis distance metrics. As a result, the Mahalanobis distance metric outperforms other metrics in noisy conditions by an average of 10% in the presence of the noise. © 2022 IEEE.

关键词： Classification (of information)

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A 16-channel Real-time Adaptive Neural Signal Compression Engine in 22nm FDSOI

A 16-channel Real-time Adaptive Neural Signal Compression En...

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Annual IEEE Northeast Workshop on circuits and systems (NEWCAS)

作者： Liyuan Guo Seyed Mohammad Ali Zeinolabedin Franz Marcus Schüffny Annika Weiße Stefan Scholze Richard George Johannes Partzsch Christian Mayr Chair of Highly-Parallel VLSI-Systems and Neuro-Microelectronics Circuits Technische Universität Dresden Germany

The real-time multi-channel intracranial recording of neural signals is required in both neuroscientific research and clinical practice. Due to the limited power budget and the increasing number of recording channels, a compression engine is highly recommended. This paper proposes a 16-channel real-time adaptive compression engine (ACE) exploiting neural signal properties. It is able to switch between lossless and near-lossless compression modes. In near-lossless mode, it compresses the spike region lossless and discards the rest. The achieved space-saving ratio (SSR) is on average about 62.5% and 91% for lossless and near-lossless modes, respectively. It can save about 78.5% of the power consumption (near-lossless compression) compared to the transmission of raw neural signals. The 16-channel ACE is implemented in 22nm FDSOI technology and consumes 230.0 μW dynamic- and 55.49 μW leakage-power at 5 MHz.

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A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI

A Low-Power Hardware Accelerator of MFCC Extraction for Keyw...

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IEEE International Conference on Artificial Intelligence circuits and systems (AICAS)

作者： Liyuan Guo Matthias Jobst Johannes Partzsch Stefan Scholze Andreas Dixius Matthias Lohrmann Seyed Mohammad Ali Zeinolabedin Christian Mayr Chair of Highly-Parallel VLSI-Systems and Neuro-Microelectronics Circuits Technische Universität Dresden Germany Centre for Tactile Internet With Human-In-The-Loop (CeTI) Technische Universität Dresden Germany

With the development of artificial intelligence, the real-time feature extraction of acoustic signals is required in a wide variety of applications, such as keyword spotting and speech recognition. Feature extraction based on Mel-frequency cepstral coefficients (MFCCs) is one of the most significant methods thereinto. A software implementation of the MFCC extraction results in relatively high power consumption and computational time limitation, often making it unsuitable for tiny battery powered devices. Therefore, an on-chip accelerator of MFCC extraction is of interest in cutting-edge scenarios. This paper presents a fixed-point low-power hardware accelerator of MFCC feature extraction implemented in 22nm FDSOI technology. It consumes an average power of 2.78µW for 1024-sample frame at a clock frequency of 1MHz. For keyword spotting, the quantized accelerator achieves an average accuracy of around 96% working along with different classification networks.

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A 10.5µW programmable SAR ADC Frontend with SC Preamplifier for Low-Power IoT Sensor Nodes 6

A 10.5µW programmable SAR ADC Frontend with SC Preamplifier...

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6th IEEE World Forum on Internet of Things, WF-IoT 2020

作者： Jotschke, Marcel Carvajal Ossa, Wilmar Reich, Torsten Mayr, Christian Fraunhofer IIS/EAS Fraunhofer Institute for Integrated Circuits Division Engineering of Adaptive Systems Dresden Germany Technische Universitaet Dresden Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits Dresden Germany

ISBN: (数字)9781728155036

ISBN: (纸本)9781728155036

Massive deployment of wireless autonomous sensor nodes requires their lifetime extension and cost reduction. The analog frontend (AFE) plays a key role in this context. This paper presents a successive approximation register analog-to-digital converter (SAR ADC) with a switched-capacitor programmable gain switched preamplifier (SCPGSA), as a basic component of an integrated ultra-low power AFE. AFE resolution, sample rate and signal gain are configurable between 6 to 13bit, 1 to 10kS/s and -6 to 12dB, respectively. The circuit draws 10.5µW from a 1.8V standard supply voltage, achieving an effective number of bits of 12.6bit and a Walden figure of merit of 169.1fJ/st. and 30.6fJ/st., computed with and without preamplifier, respectively. The circuit is employed in a modular internet of things sensor node, suitable to be solely powered from microenergy sources (energy harvesters). In order to feed charge-scaling SAR ADC inputs with the sensor voltages, typically a preamplifier stage is implemented, which can create energy overhead of magnitudes larger than the ADC power. This paper presents a duty-cycled preamplifier with programmable gain for SAR ADCs, utilizing switched-capacitor switched-opamp technique in the SCPGSA. No additional buffer circuitry is needed to charge the SAR ADC, and the preamplifier design is relaxed in power constraint. The circuit targets the low-cost internet of things market. Cost efficiency is achieved by technology choice, wide configurability and shortened ASIC design cycles. The latter results from partly generated layout, easing reuse of circuit parts from a different CMOS node. A testchip in a low-cost 180nm silicon-on-insulator technology was fabricated. © 2020 IEEE.

关键词： Sensor nodes

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SpiNNaker 2: A 10 million core processor system for brain simulation and machine learning 39

SpiNNaker 2: A 10 million core processor system for brain si...

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39th WoTUG Conference on Communicating Process Architectures, CPA 2017 and 40th WoTUG Conference on Communicating Process Architectures, CPA 2018

作者： Mayr, Christian Höppner, Sebastian Furber, Steve Highly-Parallel VLSI-Systems and Neuromorphic Circuits Institute of Circuits and Systems Technische Universitt Dresden Dresden Germany Advanced Processor Technologies Group School of Computer Science University of Manchester Manchester United Kingdom

ISBN: (纸本)9781614999485

SpiNNaker is an ARM-based processor platform optimized for the simulation of spiking neural networks. This brief describes the roadmap in going from the current SPINNaker1 system, a 1 Million core machine in 130nm CMOS, to SpiN-Naker2, a 10 Million core machine in 22nm FDSOI. Apart from pure scaling, we will take advantage of specific technology features, such as runtime adaptive body biasing, to deliver cutting-edge power consumption. Power management of the cores allows a wide range of workload adaptivity, i.e. processor power scales with the complexity and activity of the spiking network. Additional numerical accelerators will enhance the utility of SpiNNaker2 for simulation of spiking neural networks as well as for executing conventional deep neural networks. These measures should increase the simulation capacity of the machine by a factor >50. The interplay between the two domains, i.e. spiking and rate based, will provide an interesting field for algorithm exploration on SpiNNaker2. Apart from the platforms' traditional usage as a neuroscience exploration tool, the extended functionality opens up new application areas such as automotive AI, tactile internet, industry 4.0 and biomedical processing. © 2019 The authors and IOS Press. All rights reserved.

关键词： System-on-chip

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Doppler Ambiguity Resolution for Binary-Phase-Modulated MIMO FMCW Radars

Doppler Ambiguity Resolution for Binary-Phase-Modulated MIMO...

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IEEE International Conference on Radar

作者： Hector A. Gonzalez Chen Liu Bernhard Vogginger Christian G. Mayr Chair for Highly-Parallel VLSI-Systems and Neuromorphic Circuits Technische Universität Dresden Dresden Germany

ISBN: (数字)9781728126609

ISBN: (纸本)9781728137858

State-of-the-art FMCW automotive radar sensors contain Multiple-Input Multiple-Output (MIMO) arrays to obtain a good angular resolution. Binary phase modulation (BPM) is a technique used on these systems to achieve a high Signal-to-noise ratio (SNR), compared to the commonly used Time-division multiplexing (TDM). As several chirps are combined to transmit a binary code, the approach suffers from a reduced maximum unambiguous velocity. In this paper, we implement three approaches for the velocity disambiguation in a MIMO radar with four transmitters using Hadamard coding. The first two approaches require three heterogeneous frames and are based on an exact method (Chinese Remainder Theorem), and an unsupervised learning technique (Density Based Spatial Clustering of Applications with Noise) respectively. The third approach determines the true velocity by searching for the strongest response in the angular spectrum of a single frame, which suffers from a negative bias caused by the phase codes. The approaches are validated and compared in MATLAB simulations.

关键词： Chirp Transmitters Cathode ray tubes Radar Doppler effect Decoding MIMO communication

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Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS

Performance Analysis of a Comparator Based Mixed-Signal Cont...

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IFIP International Conference on Very Large Scale Integration (vlsi-SoC)

作者： Florian Protze Martin Kreißig Frank Ellinger Sebastian Höppner Stephan Hartmann Stefan H¨anzsche Stefan Scholze Georg Ellguth Christian Mayr Chair for Circuit Design and Network Theory Technische Universit¨at Dresden Dresden Germany Chair for Highly-Parallel VLSI Systems and Neuromorphic Circuits Technische Universit¨at Dresden Dresden Germany

In differential signaling systems using copper wires common mode signals are the cause of emission of electromagnetic energy. Especially in Automotive Ethernet systems this is a challenging problem. Beside classical passive components like common mode chokes active circuits can help to reduce the emission. This allows inexpensive and resource-conserving unshielded twisted pair cables to be used. This paper shows the approach of using a mixed-signal control loop based on a comparator and a 8 bit DAC for regulating the common mode voltage of an Automotive Ethernet DAC in 28 nm CMOS. An attenuation for interferers with frequencies up to 500 kHz is achieved and reaches up to 15 dB at maximum. The control loop utilizes the successive approximation algorithm commonly used for delay locked loops and DC trimming in mixed-signal circuits. In contrast to known applications the performance and usability at higher frequencies is considered in this paper. Being a nonlinear, time-variant system an analytical design of the control loop is very difficult. Therefore parametrical measurements show the dependency of frequency, amplitude and signal form of an applied common mode interferer source.

关键词： Attenuation Automotive engineering Frequency measurement White noise Voltage control Bandwidth Voltage measurement

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Spinnaker 2: A 10 million core processor system for brain simulation and machine learning

arXiv

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arXiv 2019年

作者： Mayr, Christian Hppner, Sebastian Furber, Steve Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits Institute of Circuits and Systems Technische Universitt Dresden Dresden Germany Advanced Processor Technologies Group School of Computer Science University of Manchester Manchester United Kingdom

SpiNNaker is an ARM-based processor platform optimized for the simulation of spiking neural networks. This brief describes the roadmap in going from the current SPINNaker1 system, a 1 Million core machine in 130nm CMOS, to SpiNNaker2, a 10 Million core machine in 22nm FDSOI. Apart from pure scaling, we will take advantage of specific technology features, such as runtime adaptive body biasing, to deliver cutting-edge power consumption. Power management of the cores allows a wide range of workload adaptivity, i.e. processor power scales with the complexity and activity of the spiking network. Additional numerical accelerators will enhance the utility of SpiNNaker2 for simulation of spiking neural networks as well as for executing conventional deep neural networks. These measures should increase the simulation capacity of the machine by a factor >50. The interplay between the two domains, i.e. spiking and rate based, will provide an interesting field for algorithm exploration on SpiNNaker2. Apart from the platforms' traditional usage as a neuroscience exploration tool, the extended functionality opens up new application areas such as automotive AI, tactile internet, industry 4.0 and biomedical processing. Copyright © 2019, The Authors. All rights reserved.

关键词： Deep neural networks

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