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Platform-based MPEG-4 SOC design for video communications

Journal of VLSI signal processing systems for signal, Image, and Video Technology 2006年第1期42卷 7-19页

作者： Chang, Yung-Chi Chao, Wei-Min Hsu, Chih-Wei Chen, Liang-Gee Department of Electrical Engineering Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Department of Electrical Engineering GIEE NTU Taipei Taiwan Electronics Research and Service Organization Industrial Technology Research Institute Hsinchu Taiwan IEEE CAS Technical Committee of VLSI Systems and Applications Technical Committee of Visual Signal Processing and Communications IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems IEEE CAS Technical Committee on Multimedia Systems and Applications Phi Tan Phi

An MPEG-4 video coding SOC design is presented in this paper. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented for compromise between compression performance and design cost. The proposed data reuse scheme reduces required memory access bandwidth. For texture coding path, an interleaving DCT/IDCT scheduling with substructure sharing technique is proposed. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. The cost-efficient video encoder SOC consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352×288) frames per second. © springer Science + Business Media, Inc. 2006.

关键词： Multimedia systems

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designing an embedded video processing camera using a 16-bit microprocessor for a surveillance system

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Journal of VLSI signal processing systems for signal, Image, and Video Technology 2006年第1期42卷 57-68页

作者： Sato, Koichi Evans, Brian L. Aggarwal, J.K. Department of Electrical and Computer Engineering Computer and Vision Research Center University of Texas at Austin Austin TX 78712 United States Department of Electrical and Computer Engineering Embedded Signal Processing Laboratory University of Texas at Austin Austin TX 78712 United States Department of Electrical and Computer Engineering University of Texas Austin Design and Implementation of Signal Processing Systems Technical Committee IEEE Signal Processing Society IEEE Department of Electrical and Computer Engineering Computer and Vision Research Center IEEE Computer Society

This paper describes the design and implementation of a hybrid intelligent surveillance system that consists of an embedded system and a personal computer (PC)-based system. The embedded system performs some of the image processing tasks and sends the processed data to the PC. The PC tracks persons and recognizes two-person interactions by using a grayscale side view image sequence captured by a stationary camera. Based on our previous research, we explored the optimum division of tasks between the embedded system and the PC, simulated the embedded system using dataflow models in Ptolemy, and prototyped the embedded system in real-time hardware and software using a 16-bit CISC microprocessor. This embedded system processes one 320 × 240 frame in 89 ms, which yields one-third of the rate of 30 Hz video system. In addition, the real-time embedded system prototype uses 5.7 K bytes of program memory, 854 K bytes of internal data memory and 2 M bytes external DRAM. © springer Science + Business Media, Inc. 2006.

关键词： Microprocessor chips

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Multidimensional Dsp core synthesis for FPGA

Multidimensional DSP core synthesis for FPGA

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作者： McAllister, J. Woods, R. Walke, R. Reilly, D. Queen's University Belfast Queen's Road Queen's Island Belfast BT3 9DT United Kingdom Xilinx Development Corporation 52 Mortonhall Gate Edinburgh EH16 6TJ United Kingdom Queen's University of Belfast United Kingdom IEEE Signal Processing Society Technical Committee for the Design and Implementation of Signal Processing Systems IEE Professional Network on Microelectronics and Embedded Systems

Current rapid synthesis approaches for reusable dedicated hardware components (cores) for digital signal processing systems are ineffective since they fail to capture and exploit the manner in which the resulting components are used as part of a heterogeneous system. This leads to counter-productive core redesign for each use of the core. This paper presents a solution to this issue which combines a novel but intuitive system modeling technique and associated core generation and integration methodology which generates reuable core architectures which may be optimised via algorithm level transformations. For an example design problem, these provide an effective rapid core synthesis and implementation exploration flow which allows a factor 3.9 throughput increase with no extra hardware expense. © 2006 springer Science + Business Media, LLC.

关键词： Field programmable gate arrays

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