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Model-based reasoning for electron-beam debugging of VLSI circuits

Journal of Electronic Testing 1991年第4期2卷 385-394页

作者： Marzouki, Meryem Computer Architecture Group TIM3/IMAG Laboratory Grenoble 38031 46 Av. F. Viallet France

This article deals with prototype validation of VLSI circuits. Circuits are observed using electron-beam probing used in voltage contrast mode, in such a way that grey level images are obtained and processed in order to determine potential values of connexions. These values are compared against reference values, issued from fault-free simulation of the device under test. The list of discrepancies resulting from comparison constitutes input for a fault localization process done using a knowledge-based system. In this article, the reasons for the choice of such an approach are explained, the approach itself is described, as well as its implementation and the obtained results. © 1991 Kluwer Academic Publishers.

关键词： Electron-beam testing model-based reasoning second generation KBS VLSI circuit diagnosis

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A Fail-Safe Microcontroller for Railway Signalling

A Fail-Safe Microcontroller for Railway Signalling

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European Conference on Solid-State Circuits (ESSCIRC)

作者： G. Chaumontet V. Castro Alves M. Nicolaidis A. Guyot B. Courtois TIM3 LABORATORY COMPUTER ARCHITECTURE GROUP IMAG Grenoble France

In this paper, we describe an architecture of a microcontroller called MAPS which answers the safety criterions of the signalling railway industries. MAPS has been designed by using, on the same chip and for the first... 详细信息

关键词： Microcontrollers Rail transportation Circuit faults Railway safety Circuit testing Switches Actuators Very large scale integration computer architecture Relays

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SELF-EXERCISING CHECKERS FOR UNIFIED BUILT-IN SELF-TEST (UBIST)

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IEEE TRANSACTIONS ON computer-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1989年第3期8卷 203-218页

作者： NICOLAIDIS, M Computer Architecture Group IMAG/TIM3 Laboratory Grenoble France

An original built-in self-test (BIST) scheme is proposed aimed at covering some of the shortcomings of self-checking circuits and applicable to all tests needed for integrated circuits. In this scheme, self-checking techniques and built-in self-test techniques are combined in an original way to take advantage of each other. The result is a unified BIST scheme (UBIST), allowing high fault coverage for all tests needed for integrated circuits, e.g., offline test (design verification, manufacturing test, maintenance test) and online concurrent error detection. An important concept introduced is that of self-exercising checkers. The strongly code-disjoint property of the checkers is ensured for a very large class of fault hypotheses by internal test pattern generation, and the design of the checkers is simplified.< >

关键词： Built-in self-test Circuit testing Circuit faults Integrated circuit testing Automatic testing Proposals Integrated circuit manufacture Test pattern generators Hardware Redundancy

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Debugging integrated circuits: AI can help

Debugging integrated circuits: AI can help

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European Test Conference

作者： M. Marzouki B. Courtois Computer Architecture Group IMAG/TIM3 Laboratory Grenoble France

An overview of Pesticide, a Prolog-written expert system for integrated-circuit debugging is presented. Pesticide relies on the knowledge of structural and functional properties of both combinational and sequential ICs. Its external environment consists of a scanning electron microscope used in voltage contrast mode and linked to CAD tools. Particular attention is given to the modeling of the device under test, the strategies adopted for fault detection and localization within the circuit under test, and some simple execution examples.< >

关键词： Debugging Artificial intelligence Circuit testing System testing Automatic testing Diagnostic expert systems Very large scale integration Circuit simulation Expert systems Databases

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Fault simulation and test pattern generation at the multiple-valued switch level

Fault simulation and test pattern generation at the multiple...

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IEEE International Test Conference

作者： J.-P. Caisso B. Courtois VLSI Design Laboratory of the Electrical Engineering Dpt. McGill University Montreal Canada IMAG/TIM3-Computer Architecture Group Grenoble France

A fault simulation and test-pattern-generation environment is specified. It includes a multiple-valued algebra, allows the natural treatment of loops and bidirectional devices, and models the physical failures. The authors' main idea is to define what is possible when no extraction to gate level and no creation of transistor groups are performed. Two fault groups are distinguished: the faults which can be modelled in a downward layout, and the faults which can be modelled in an upward verification. This distinction induces difference in the switch network obtained, as the second group allows to model the line resistances.< >

关键词： Switches Test pattern generators Circuit faults Circuit simulation Circuit testing Computational modeling Algebra Semiconductor device modeling Switching circuits computer architecture

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Electron Beam Sensitive Devices Design Methods

Electron Beam Sensitive Devices Design Methods

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European Conference on Solid-State Circuits (ESSCIRC)

作者： D. Micollet B. Courtois IMAG TIM3 COMPUTER ARCHITECTURE GROUP GRENOBLE France

two methods are detailled for the design of e - beam sensitive devices for controlability.

关键词： Electron beams Design methodology Voltage Polarization Inverters Observability MOS devices computer architecture Integrated circuit testing Design automation

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Electron Beam Observability and Controlability for the Debugging of Integrated Circuits

Electron Beam Observability and Controlability for the Debug...

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European Conference on Solid-State Circuits (ESSCIRC)

作者： I. Guiguet D. Micollet J. Laurent B. Courtois COMPUTER ARCHITECTURE GROUP IMAG/TIM3 Grenoble France

Observability and controlability using an electron beam are addressed in this paper. For observability, a link between a CALMA description and a Scanning Electron Microscope (SEM), based on a superimposition technique, is detailled. For controlability, a study of the Electron Beam Induced Current (EBIC) phenomenon in a diffused diode is presented.

关键词： Electron beams Observability Debugging Scanning electron microscopy Automatic voltage control Electron emission Circuit testing Adaptive arrays Logic arrays Automatic testing

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EVALUATION OF A SELF-CHECKING VERSION OF THE MC 68000 MICROPROCESSOR.

EVALUATION OF A SELF-CHECKING VERSION OF THE MC 68000 MICROP...

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Digest of Papers - FTCS 15, Fifteenth Annual International Symposium on Fault-Tolerant Computing.

作者： Nicolaidis, M. IMAG/TIM3 Computer Architecture Group Grenoble Fr IMAG/TIM3 Computer Architecture Group Grenoble Fr

ISBN: (纸本)0818606185

Rules for the design of self-checking circuits, based on fault hypotheses at the transistor level, are given. The rules are applied to a self-checking version of the control section of the MC 68000 microprocessor. Other methods proposed in the literature for designing self-checking sequencers are compared with the present method. Some new results on the design of self-checking ROMs, PLAs, and arithmetic units are presented.

关键词： computerS, MICROcomputer

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UPDATING FUNCTIONAL FAULT MODEL FOR MICROPROCESSOR INTERNAL BUSES.

UPDATING FUNCTIONAL FAULT MODEL FOR MICROPROCESSOR INTERNAL ...

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Digest of Papers - FTCS 15, Fifteenth Annual International Symposium on Fault-Tolerant Computing.

作者： Marchal, P. IMAG/TIM3 Computer Architecture Group Grenoble Fr IMAG/TIM3 Computer Architecture Group Grenoble Fr

ISBN: (纸本)0818606185

Functional fault hypotheses for testing complex microprocessors are discussed. Functional testing generally requires information such as register-level architecture and the instruction set, rather than a detailed gate-level description. For the specific case of a microprocessor internal bus, not only a gate-level description is needed, but also an electrical simulation to determine functional hypotheses. Complete functional fault hypotheses for testing of internal bus malfunctions for all popular microprocessors are given. The hypotheses are also applicable to wafer scale integration, where the use of buses is quite extensive.

关键词： computerS, MICROcomputer

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EFFICIENT BUILT-IN SELF TEST SCHEME FOR FUNCTIONAL TEST OF EMBEDDED RAMS.

EFFICIENT BUILT-IN SELF TEST SCHEME FOR FUNCTIONAL TEST OF E...

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Digest of Papers - FTCS 15, Fifteenth Annual International Symposium on Fault-Tolerant Computing.

作者： Nicolaidis, M. IMAG/TIM3 Computer Architecture Group Grenoble Fr IMAG/TIM3 Computer Architecture Group Grenoble Fr

An efficient built-in self-testing scheme for RAMs using mechanisms integrated into the chip are described. The scheme is based on quasi/marching algorithms. New schemes are introduced for LFSR applications.

ISBN: (纸本)0818606185

关键词： AUTOMATIC TESTING

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