The draft international standard ITU-T H.263 is closely related to the well known and widely used ITU-T Recommendation H.261. However, H.263 does provide the same subjective image quality at less than half the bit-rat...
The draft international standard ITU-T H.263 is closely related to the well known and widely used ITU-T Recommendation H.261. However, H.263 does provide the same subjective image quality at less than half the bit-rate. In this paper we investigate to what extend single enhancements of H.263 contribute to this performance gain, and consider the trade-off quality vs. complexity. Based on typical test sequences, H.263 with its various modes is compared to H.261 on the basis of rate distortion curves at bit-rates up to 128 kbps. At 64 kbps, the performance gain of H.263 in its default mode compared to H.261 is approximately 2 dB. This improvement is achieved with only little increase of complexity, and is mainly due to more accurate motion compensation with half-pel accuracy. Considering the trade-off quality vs. complexity, the combination of the optional coding-modes "Advanced prediction mode" and "PB-frames mode" is a good compromise, resulting in an additional performance gain of 1.5 dB PSNR at 64 kbps. The "Syntax-based arithmetic coding mode" on the other hand, offers only a very small performance gain (0.1 dB at 64 kbps) for its increased computational complexity. Results from profiling an H.263 software codec are presented in order to support complexity considerations of the optional coding-modes.
We address the problem of coherent detection of a signal embedded in heavy-tailed noise modeled as a subGaussian, alpha-stable process. We assume that the signal is a complex-valued vector of length L, known only with...
详细信息
We address the problem of coherent detection of a signal embedded in heavy-tailed noise modeled as a subGaussian, alpha-stable process. We assume that the signal is a complex-valued vector of length L, known only within a multiplicative constant. The dependence structure of the noise, i.e., the underlying matrix of the sub Gaussian process, is not known. The intent is to implement a generalized likelihood ratio detector which employs robust estimates of the unknown noise underlying matrix and the unknown signal strength. The performance of the proposed adaptive detector is compared to that of an adaptive matched filter that uses Gaussian estimates of the noise underlying matrix and the signal strength and is found to be clearly superior. The proposed new algorithms an evaluated via Monte-Carlo simulation.
作者：
Minami, TKasai, RMatsuda, HKusaba, RMemberNTT LSI Laboratories
Atsugi Japan 243-01 Graduated in 1980 from the Department of Electrical Engineering
Kyushu University where he received his Master's degree in 1982 and joined NTT. Until March 1986 he was engaged in the development of application software for electronic switching systems. He then engaged in research and development of LSIs for image signal processing. At present he is Senior Research Engineer Advanced LSI Laboratory NTT LSI Laboratories. He is a member of IEEE. Graduated in 1972 from the Department of Electrical Engineering
Osaka University where he received his Master's degree in 1974 and his Ph.D. in 1992. He joined NTT in 1974. He is engaged in research and development of analysis of MOS devices and design of ASIC for communication. At present he is Executive Research Engineer Advanced LSI Laboratory NTT LSI Laboratories. He is a member of IEEE. Graduated in 1987 from the Department of Communications
Tohoku University where he received his Master's degree in 1989 and joined NTT. He is engaged in research and development of high-speed design for image processing LSIs. At present he is Research Engineer Advanced LSI Laboratory NTT LSI Laboratories. He is a member of the Information Processing Society. Graduated in 1985 from the Department of Electrical Engineering
Keio University where he received his Master's degree in 1987 and joined NTT. He is engaged in CAD research. At present he is Senior Research Engineer Advanced LSI Laboratory NTT LSI Laboratories. He is a member of the Information Processing Society and IEEE.
This paper discusses the downsizing and speed improvement of short-word multiplier-accumulators, which are frequently used in digital signal processors. As a first step, the optimal configuration for an array-type car...
详细信息
This paper discusses the downsizing and speed improvement of short-word multiplier-accumulators, which are frequently used in digital signal processors. As a first step, the optimal configuration for an array-type carry-save adder is considered where the shortest path in the full-adder is used to propagate the sum signal and the carry signal is sent to the full-adder of the two lower stages by skipping a stage. A configuration of the full-adder suitable for the structure is proposed. The case of eight partial product additions shows that the delay can be reduced by 22 percent compared to a simple array-type carry-save adder. Then the short-word carry look-ahead adder using the pass-transistor logic is considered. It is shown that a single-stage carry look-ahead circuit with a four-bitwise iterative structure exhibits nearly the same delay as a two-stage carry look-ahead circuit. In other words, the former is better suited to downsizing. This paper intends to examine the effectiveness of the foregoing new array-type carry-save adder and the single-stage carry look-ahead circuit using the 0.5-mu m CMOS technology. A 16-bit x 14-bit + 31-bit multiplier-accumulator has been designed and is evaluated for cases where the array-type carry-save adder is used to handle accumulation as well as partial products. The resulting area and delay are 0.77 x 0.78 mm(2) and 6.8 ns, respectively. The effectiveness of the approach used in this paper is evaluated by constructing a multiplier-accumulator, but the method is also useful in constructing a multiplier.
暂无评论