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Conference on Design and Architectures for Signal and image processing

作者： Paolo Meloni Image Processing on Embedded Systems University of Cagliari IT

image processing algorithms in today electronics market pose the need for increasing computation capabilities at a limited power budget. Modern applications in the robotics and cyber-physical systems domains require image acquisition, analysis and information extraction to be executed on embedded low-power, portable and autonomous devices, requiring novel architecture solutions to be studied and implemented. The papers in this session present three design cases targeting edge-cutting applications, exploiting heterogeneous embedded computing platforms.

关键词： image processing Algorithm design and analysis Robots Computer architecture Real-time systems embedded systems Consumer electronics

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Self-Awareness for Autonomous systems

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PROCEEDINGS OF THE IEEE 2020年第7期108卷 971-975页

作者： Dutt, Nikil Regazzoni, Carlo S. Rinner, Bernhard Yao, Xin Nikil Dutt (Fellow IEEE) received the Ph.D. degree from the University of Illinois at Urbana–Champaign Champaign IL USA in 1989.""He is currently a Distinguished Professor of computer science (CS) cognitive sciences and electrical engineering and computer sciences (EECS) with the University of California at Irvine Irvine CA USA. He is a coauthor of seven books. His research interests include embedded systems electronic design automation (EDA) computer architecture distributed systems healthcare Internet of Things (IoT) and brain-inspired architectures and computing.""Dr. Dutt is a Fellow of ACM. He was a recipient of the IFIP Silver Core Award. He has received numerous best paper awards. He serves as the Steering Committee Chair of the IEEE/ACM Embedded Systems Week (ESWEEK). He is also on the steering organizing and program committees of several premier EDA and embedded system design conferences and workshops. He has served on the Editorial Boards for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and the ACM Transactions on Embedded Computing Systems and also previously served as the Editor-in-Chief (EiC) for the ACM Transactions on Design Automation of Electronic Systems. He served on the Advisory Boards of the IEEE Embedded Systems Letters the ACM Special Interest Group on Embedded Systems the ACM Special Interest Group on Design Automationt and the ACM Transactions on Embedded Computing Systems. Carlo S. Regazzoni (Senior Member IEEE) received the M.S. and Ph.D. degrees in electronic and telecommunications engineering from the University of Genoa Genoa Italy in 1987 and 1992 respectively.""He is currently a Full Professor of cognitive telecommunications systems with the Department of Electrical Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa and a Co-Ordinator of the Joint Doctorate on Interactive and Cognitive Environments (JDICE) international Ph.D. course started initially as EU Erasmus Mundus Project and

Autonomous systems are able to make decisions and potentially take actions without direct human intervention, which requires some knowledge about the system and its environment as well as goal-oriented reasoning. In computer systems, one can derive such behavior from the concept of a rational agent with autonomy (“control over its own actions”), reactivity (“react to events from the environment”), proactivity (“act on its own initiative”), and sociality (“interact with other agents”) as fundamental properties \n[1]\n. Autonomous systems will undoubtedly pervade into our everyday lives, and we will find them in a variety of domains and applications including robotics, transportation, health care, communications, and entertainment to name a few. \nThe articles in this month’s special issue cover concepts and fundamentals, architectures and techniques, and applications and case studies in the exciting area of self-awareness in autonomous systems.

关键词： Special issues and sections Autonomous systems Self-aware Robot sensing systems Computational modeling

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A 4k capable FPGA based high throughput binary arithmetic decoder for H.265/MPEG-HEVC

A 4k capable FPGA based high throughput binary arithmetic de...

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IEEE International Conference on Consumer Electronics - Berlin (ICCE-Berlin)

作者： Jan Hahlbeck Benno Stabernack Image Processing Department Embedded Systems Group Berlin Germany

High Efficiency Video Coding (HEVC) is the newest video coding standard approved by the ISO/IEC and ITU-T in January 2013. By providing a video coding efficiency gain of up to 50% compared to its predecessor H.264/MPEG-4 AVC, the complexity of the used algorithms has raised significantly. Targeting video formats with higher spatial and temporal resolutions - e.g. 4Kp60 in broadcast applications - make implementing encoders and decoders a challenging task. A well known bottleneck in the decoder architecture is the Context-Based Adaptive Binary Arithmetic Coding (CABAC), specified as entropy coding method in the H.265/MPEG-HEVC standard. Reaching high throughput for real time applications is a demanding task in terms of context modeling and serial bin-to-bin dependencies in the binary arithmetic coding engine. Especially the context selection and the update of the context model in binary decision mode requires a complex underlying control flow for the decoding process of each syntax element. This paper presents a pure hardware implementation of a Main Profile H.265/MPEG-HEVC compliant entropy decoder. The design has been optimized to achieve real time performance up to 4k video resolutions. By using state-of-the-art FPGA technology, data rates of up to 104 MBit/s can be achieved.

关键词： Decoding Context Video coding Transform coding Entropy Context modeling Syntactics

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Memory access analysis and optimization of a parallel H.264/SVC decoder for an embedded multi-core platform

Memory access analysis and optimization of a parallel H.264/...

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2013 7th Conference on Design and Architectures for Signal and image processing, DASIP 2013

作者： Brandenburg, Jens Stabernack, Benno Fraunhofer Institute for Telecommunications Image Processing Department Embedded Systems Group Einsteinufer 37 10587 Berlin Germany

ISBN: (纸本)9791092279016

HW/SW co-design and optimization requires an in-depth performance and bottleneck analysis of the developed system. Due to the increasing gap between the performance of the processing elements and the memory subsystem also memory access analysis plays an important role in this optimization task. This is especially the case for state of the art media signal processing applications, like video decoders, with their growing demand for high memory bandwidths and low latency data accesses. Optimizing memory partitioning, memory hierarchy, memory characteristics and allocation of data structures formulates a multidimensional HW/SW co-optimization problem with increasing complexity due to the trend towards embedded multi-core platforms. In order to aid the developer with these optimization tasks, performance and memory access analysis tools are needed. Nowadays there exist many different vendor specific debug and profiling tools for different processor architectures addressing different aspects of the overall co-optimization problem. Moving to heterogeneous platforms makes the combination and integration of the different profiling data a challenging task. Moreover it is important to combine the profiling results with information gathered from dedicated components, like interrupts, signals and/or synchronization events, representing the actual hardware platform. To overcome this issue we propose a flexible tracing and profiling methodology capable to trace all hardware aspects of the modeled simulation platform. Based on this methodology we developed a tool, which gives a comprehensive overview of the software tasks running on the various processing elements of the particular execution platform. Furthermore our tool provides detailed non-intrusive memory access and performance analyses based on SystemC virtual platform simulation models for heterogeneous embedded multi-core platforms. A demonstration of the tools capabilities is given by an exemplary analysis of a Scalable Vi

关键词： Video signal processing

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High speed embedded imaging architectures for multichannel imaging

High speed embedded imaging architectures for multichannel i...

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Imaging systems and Applications, ISA 2013

作者： Schwannecke, Hans-Christian Rosenberger, Maik Schellhorn, Mathias Linß, Gerhard University of Technology Ilmenau Department Quality assurance and Industrial Image Processing Embedded Systems Group Gustav Kirchhoff Platz 2 98693 Ilmenau Germany

Multichannel imaging is a key technology for new application fields. Therefore a new parallel image processing architecture was designed. The new platform allows fast processing speed and solves problems in multispect... 详细信息

ISBN: (纸本)9781557529756

关键词： Imaging systems

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HEVC performance and complexity for 4K video

HEVC performance and complexity for 4K video

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IEEE International Conference on Consumer Electronics - Berlin (ICCE-Berlin)

作者： Benjamin Bross Valeri George Mauricio Alvarez-Mesa Tobias Mayer Chi Ching Chi Jens Brandenburg Thomas Schierl Detlev Marpe Ben Juurlink Image Processing Department Fraunhofer HHI Berlin Germany Embedded Systems Architecture Group Technical University of Berlin Berlin Germany

The recently finalized High-Efficiency Video Coding (HEVC) standard was jointly developed by the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG) to improve the compression performance of current video coding standards by 50%. Especially when it comes to transmit high resolution video like 4K over the internet or in broadcast, the 50% bitrate reduction is essential. This paper shows that real-time decoding of 4K video with a frame-level parallel decoding approach using four desktop CPU cores is feasible.

关键词： Decoding Standards Bit rate Video coding Real-time systems Workstations Streaming media

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Memory access analysis and optimization of a parallel H.264/SVC decoder for an embedded multi-core platform

Memory access analysis and optimization of a parallel H.264/...

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Conference on Design and Architectures for Signal and image processing

作者： Jens Brandenburg Benno Stabernack Fraunhofer Institute for Telecommunications Heinrich Hertz Institute Image Processing Department Embedded Systems Group Einsteinufer 37 10587 Berlin Germany

关键词： Data models Data collection Adaptation models Analytical models Static VAr compensators Decoding Kernel

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