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Improved parallel approximation of a class of integer programming problems 23rd

23rd International Colloquium on Automata, Languages, and programming, ICALP 1996

作者： Alon, Noga Srinivasan, Aravind School of Mathematical Sciences Tel Aviv University Tel Aviv69978 Israel Dept. Of Information Systems and Computer Science National University of Singapore Singapore119260 Singapore

ISBN: (纸本)3540614400

We present a method to derandomize RNC algorithms, converting them to NC algorithms. Using it, we show how to approximate a class of iVP-hard integer programming problems in NC, to within factors better than the current-best NC algorithms (of Berger &c Rompel and Motwani, Naor & Naor);in some cases, the approximation factors are as good as the best-known sequential algorithms, due to Raghavan. This class includes problems such as global wire-routing in VLSI gate arrays. Also for a subfamily of the "packing" integer programs, we provide the first NC approximation algorithms;this includes problems such as maximum matchings in hypergraphs, and generalizations. The key to the utility of our method is that it involves sums of superpolynomially many terms, which can however be computed in NC;this superpolynomiality is the bottleneck for some earlier approaches. © Springer-Verlag Berlin Heidelberg 1996.

关键词： Approximation algorithms

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An extension of the Lovász local lemma, and its applications to integer programming 96

An extension of the Lovász local lemma, and its application...

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Proceedings of the seventh annual ACM-SIAM symposium on Discrete algorithms

作者： Aravind Srinivasan Dept. of Information Systems & Computer Science National University of Singapore Singapore 119260

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A parallel debugger with support for distributed arrays, multiple executables and dynamic processes 6th

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6th International Conference on Compiler Construction, CC 1996

作者： Fritzson, Peter Wismüller, Roland Hansen, Olav Sala, Jonas Skov, Peter PELAB Dept. of Computer and Information Science Linköping University LinköpingS-581 83 Germany Department of Computer Science University of Technology MunichMünchenD-802 90 Germany Parsytec Gmbh Jülicher Strasse 338 AachenD-52070 Germany Parallel Systems Dalvägen 8 SolnaS-171 23 Sweden

ISBN: (纸本)9783540610533

In this paper we present the parallel debugger DETOP with special emphasis on new support for debugging of programs with distributed data structures such as arrays that have been partitioned over a number of processors. The new array visualizer within DETOP supports transparent browsing and visualization of distributed arrays which occur in languages such as High Performance Fortran. Visualization of sparse arrays is supported through an array mapper facility, as well as transparent visualization of arrays which have been partitioned by hand for applications in C or Fortran77. Color coding makes the visualization more expressive and easier to read. DETOP provides a graphical user interface that is simple to use even for inexperienced users and supports not only static data parallel programs, but also dynamic programs and parallel applications based on functional decomposition. The combination of support for applications that include dynamic process creation, multiple executables, processes and threads, and distributed data structures, makes DETOP rather unique among parallel debuggers. DETOP has been implemented for Parsytec PowerPC based multicomputers with Sparcstation frontends. Ongoing efforts include portable versions of DETOP for PVM and MPI run-time environments. © Springer-Verlag Berlin Heidelberg 1996.

关键词： Visualization

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A method of post-processing for character recognition based on syntactic and semantic analysis of sentences

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systems AND computerS IN JAPAN 1996年第9期27卷 94-107页

作者： Kise, K Shiraishi, T Takamatsu, S Fukunaga, K College of Engineering University of Osaka Prefecture Sakai Japan 593 Currently with Mitsubishi Electric Corp. Shinobu Takamastu:graduated in 1971 from the Dept. Electrical Eng. Coll. Eng. Univ. of Osaka Pref. where he received his Master's degree in 1973 and his Dr. of Eng. degree later. At present Assoc. Prof. Dept. Computer and Systems Sciences or C.S.S. Univ. of Osaka Pref. He is engaged in research on natural language understanding knowledge information processing and specification description language. He is a member Inf. Proc. Soc. and Soc. Artif. Intel. Member

Post-processing of character recognition refers to the processing used to correct the errors in character recognition. When the input is a string representing a sentence in the highly precise error correction, it is desired that the syntactic as well as semantic examinations should be made at the sentence level. This paper assumes that the morphemes, syntax and semantics of the input sentence can be analyzed, and proposes a method that uses the syntactic and semantic analysis in the post-processing. The proposed method receives the list of candidate characters up to the fifth, and outputs the sentence that is adequate from the viewpoints of both syntax and semantics. The method features the following three points: (1) in word matching, it is examined also whether or not a sentence adequate from the viewpoints of syntax and semantics can he composed, and then the inadequate words extraction is inhibited;(2) characters having stronger syntactic and semantic constraints, such as the single-character particle and the conjugational suffix, are estimated top-down. Then, the case where the adequate character is not contained in the candidates can be handled;and (3) the words for which the adequateness cannot be determined from the syntactic or semantic viewpoint are selected by character re-recognition processing. An experiment is executed for 50 sample sentences. The character recognition rate is improved from 83.0 percent to 98.0 percent, and the sentence recognition rate is improved from 10.0 percent to 94.0 percent. Compared to the method based only on word matching, the sentence recognition rate is improved by more than 20 percent. In other words, the effectiveness of the proposed method is demonstrated.

关键词： character recognition postprocessing document image processing document image recognition natural language processing

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A dynamic fuzzy reasoning method for adaptive diagnostic systems design

A dynamic fuzzy reasoning method for adaptive diagnostic sys...

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Conference of the North American Fuzzy information Processing Society - NAFIPS

作者： M. Ulieru M.H. Smith Department of Computer Science and Information Systems Brunel University UK School of Engineering Science Simon Fraser University Burnaby BC Canada Dept. of Electrical Engineering and Computer Science University of California Berkeley USA Dept. of Mining and Mineral Process Engineering University of British Columbia Canada

Tackles some critical issues in diagnostic problem solving by addressing the conceptual design of automatic diagnostic systems able to cope with complex dynamic processes. The dynamic switching fuzzy system model introduced by M.H. Smith (1994) is used as a generalized framework which dynamically changes the reasoning method by tuning the operators and/or defuzzification methods. This technique is applied to tune different fuzzy diagnostic models introduced by M. Ulieru (1995). The dynamic switching fuzzy diagnostic model (DFSDM) proposed in this paper can adapt online to drastic changes in the behavior of the diagnosed process. Tutorial investigations on an inverted pendulum clarify the ability of this method to cope with unexpected, unknown disturbances while simulation results on an electromechanical process prove the ability of this technique to manage critical faults in continuous dynamic systems.

关键词： Fuzzy reasoning Adaptive systems Fuzzy systems computer science Design engineering Electronic mail Problem-solving Degradation information systems Minerals

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Providing high availability in very large workflow management systems

Providing high availability in very large workflow managemen...

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5th international conference on Extending Data Base Technology, EDBT 1996

作者： Kamath, M. Alonso, G. Günthör, R. Mohan, C. Dept. of Computer Science University of Massachusetts Amherst MA 01003 United States Institute for Information Systems Database Group ETH Zentrum CH-8092 Zürich Switzerland IBM European Networking Center Vangerowstr. 18 69115 Heidelberg Germany IBM Almaden Research Center 650 Harry Road San Jose CA 95120 United States

ISBN: (纸本)354061057X

Workflow management systems (WFMS) support the modeling, coordinated execution and monitoring of business processes within an organization. In particular, very large workflow management systems are used in organizations with several thousand users, hundreds of thousands of process instances, and several thousand sites, all distributed over wide geographic areas. In these environments, failure of the WFMS or the underlying workflow database which stores the meta-information about the processes is not tolerable. This paper addresses the problem of providing high availability in workflow management systems by proposing a backup technique which ensures that execution of a process instance can be resumed at any point in time in the event of a failure. An essential characteristic of our backup scheme is that it allows the user to define different availability levels, reducing the cost of maintaining backups. The backup scheme is implemented using the workflow semantics, which we believe will (i) make it independent of the underlying workflow database, thus permitting the use of heterogeneous databases as primary and backup, (ii) reduce overheads, especially when compared to backup schemes provided by database systems.

关键词： Database systems

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Test processor ASIC design

Test processor ASIC design

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IEEE International Conference on Semiconductor Electronics (ICSE)

作者： L. Ali Z.M. Darus M.A.M. Ali I. Ahmed Dept. of Electr. Electron. & Syst. Eng. Univ. Kebangsaan Malaysia Department of Electrical Electronic and Systems Engineering Universiti Kebangsaan Malaysia Malaysia Faculty of Computer Science and Information Technology University of Malaya Malaysia

In this paper, a design of a test processor ASIC employing a probabilistic approach is presented. The test processor chip is computer programmable. It consists of linear feedback shift register (LFSR) which can select one of 16 polynomials and set user programmable need for every test set, signature analyzer and 3 built-in RAMs and other control circuitry. It is capable of generating random numbers and applying them to the circuit under test (CUT) and then retrieve the responses from the CUT. It can generate a signature by compressing the response data and detect circuit faults by comparing this signature with that of a good CUT. This ASIC can be used to design a low cost IC tester of reliable performance.

关键词： Application specific integrated circuits Process design Circuit testing Linear feedback shift registers Polynomials Linear feedback control systems Feedback circuits Random number generation Electrical fault detection Fault detection

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A Wearable computer for Use in Microgravity Space and Other Non-Desktop Environments 96

A Wearable Computer for Use in Microgravity Space and Other ...

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1996 Conference Companion on Human Factors in Computing systems, CHI 1996

作者： Matias, Edgar MacKenzie, I. Scott Buxton, William The Matias Corporation 178 Thistledown Boulevard RexdaleONM9V 1K1 Canada Dept. of Computing and Information Science University of Guelph GuelphONN1G 2W1 Canada University of Toronto Xerox PARC C/o Computer Systems Research Institute University of Toronto TorontoONM5S 1A4 Canada

We present one possible design for a "wearable" computer-a computer that is worn. Our prototype permits text entry without the need of a table or other supporting surface. Typing can be performed while stand... 详细信息

ISBN: (纸本)9780897918329

关键词： Microcomputers

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Supporting the specification and analysis of timing constraints

Supporting the specification and analysis of timing constrai...

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Real-Time Technology and Applications Symposium

作者： Lo Ko C. Healy E. Ratliff R. Arnold D. Whalley M. Harmon Computer Science Department Florida State University Tallahassee FL USA Florida State University Tallahassee FL US Dept. of Comput. Sci. Florida State Univ. Tallahassee FL USA Computer and Information Systems Department Florida Agricultural and Mechanical University Tallahassee FL USA

Real-time programmers have to deal with the problem of relating timing constraints associated with source code to sequences of machine instructions. This paper describes an environment to assist users in the specification and analysis of timing constraints. A user is allowed specify timing constraints within the source code of a C program. A user interface for a timing analyzer was developed to depict whether these constraints were violated or met. In addition, the interface allows portions of programs to be quickly selected with the corresponding bounded times, source code lines, and machine instructions automatically displayed The result is a user-friendly environment that supports the user specification and analysis of timing constraints at a high (source code) level and retains the accuracy of low (machine code) level analysis.

关键词： Timing Performance analysis High level languages Optimizing compilers computer science Electronic mail programming profession User interfaces Real time systems Pipelines

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The congruence between a firm's competitive strategy and information technology leader's rank and role

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Journal of Management information systems 1996年第1期13卷 63-88页

作者： Karimi, J. Gupta, Y.P. Somers, T.M. Department of Information Systems College of Business University of Colorado Denver CO United States University of Arizona Tucson AZ United States University of Hong Kong Department of Computer Science Association for Computing Machinery Computing Society Society for Information Management College of Business University of Colorado Denver CO United States University of Louisville University of Manitoba University of Bradford United Kingdom Dept. of Fin. and Business Economics Wayne State University Bowling Green State University University of Toledo DSI POMS INFORMS

Today's firms are faced with new competitive and technological challenges. As a consequence, many senior executives are looking for information technology (IT) leaders who not only can understand technology but also can comprehend technology's potential to affect business strategy. For the IT leaders, rising to such numerous, and often conflicting, challenges is not easy. Indeed, there is a higher than average corporate dismissal rate and shorter tenure for IT leaders compared with other top executives. Based on the responses from 213 IT leaders in the financial services industry, this study found that the rank and role of a firm's IT leader must be aligned with the firm's competitive strategy. The implications of the findings for the firms' executives, as well as researchers, are discussed in detail.

关键词： Competitive strategy information technology leaders Strategy-technology alignment

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