In this paper, we propose a fast iterative modular multiplication algorithm for calculating the product AB modulo N, where N is a large modulus in number-theoretic cryptosystems, such as RSA cryptosystems. Our algorit...
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In this paper, we propose a fast iterative modular multiplication algorithm for calculating the product AB modulo N, where N is a large modulus in number-theoretic cryptosystems, such as RSA cryptosystems. Our algorithm requires (5/3-1/4k)n/k+5/3 4k-1/3 2k-17/6 additions on average for an n-bit modulus if k carry bits are dealt with in each loop. For a 512-bit modulus, the known fastest modular multiplication algorithm, Chen and Liu's algorithm, requires 517 additions on average. However, comp.red to Chen and Liu's algorithm, our algorithm reduces the number of additions by 26% for a 512-bit modulus.
A pixel-parallel image processor provides the capability for desktop systems to perform low-level image processing tasks in real time. comp.ct logic units are pitch-matched to DRAM columns to form dense blocks of proc...
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A pixel-parallel image processor provides the capability for desktop systems to perform low-level image processing tasks in real time. comp.ct logic units are pitch-matched to DRAM columns to form dense blocks of processing elements. The processing elements are interconnected to form a 64 × 64 array, with each processing element assigned to a single pixel. Operating with a 60-ns clock cycle in a comp.ete system, fully functional devices dissipate 300 mW. Using the devices, low-level image processing tasks have been performed in real time with input images provided at rates exceeding 30 frames/s.
A box constrained variational inequality problem can be reformulated as an unconstrained minimization problem through the D-gap function. Some basic properties of the affine variational inequality subproblems in the c...
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A box constrained variational inequality problem can be reformulated as an unconstrained minimization problem through the D-gap function. Some basic properties of the affine variational inequality subproblems in the classical Josephy-Newton method are studied. A hybrid Josephy-Newton method is then proposed for minimizing the D-gap function. Under suitable conditions, the algorithm is shown to be globally convergent and locally quadratically convergent. Some numerical results are also presented.
A shear-force sensitive silicon sensor is developed using microfabrication technology. Four ion implanted piezoresistive resistors are embedded in a silicon diaphragm and used as independent strain gauges. An epoxy me...
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ISBN:
(纸本)0791816346
A shear-force sensitive silicon sensor is developed using microfabrication technology. Four ion implanted piezoresistive resistors are embedded in a silicon diaphragm and used as independent strain gauges. An epoxy mesa is added on top of the diaphragm to transmit force from the load to the diaphgram. Both the shear and normal comp.nents of an applied force can be resolved by measuring the resistance variations of the four resistors. The sensor is tested when a 0-3 N variant force is applied at elevation angles of 0° (normal), 30°, 45° and 60°. At each elevation angle, the sensor rotates from 0° to 360° at an increment of 30°. Good linearity (R > 0.98) and high repeatability (standard deviation < 8%) are observed. Both normal and shear sensitivities are measured. The shear sensitivity is characterized in terms of both magnitude and direction of the applied force. The results show that the sensor has a high sensing ability to both normal and shear forces (comp.red to commercial load cell). In this paper, the sensor design, fabrication and testing are described. The sensor characterization and shear sensing ability are discussed.
As the number of neurons in an Back-propagation Artificial Neural Network (ANN) increases, learning time needed to train the ANN increases considerably. Therefore, attention has been focused on design schemes to execu...
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As the number of neurons in an Back-propagation Artificial Neural Network (ANN) increases, learning time needed to train the ANN increases considerably. Therefore, attention has been focused on design schemes to execute Back-propagation algorithm in parallel, in order to take advantage of inherent parallelism in the algorithm. In this paper, a systolic array which executes forward-backward propagation of the Back-propagation algorithm in parallel is designed. In order to do this, (1) inherent parallelism and regular data flow of the forward-backward propagation are analyzed. From this analysis, (2) data dependency graphs are obtained and (3) the input period of each input pattern and indices of each variable are calculated. The proposed systolic array does not have long feedback links which cause time skew. It exploits the implicit parallelism of the back-propagation algorithm, reduces the number of processing elements (PEs) and the number of idle PEs. The processing time needed to train the ANN can therefore be reduced considerably. It is shown that the proposed systolic array increases PE utilization (reduces execution time) considerably.
Virtual paths (VPs) in an ATM network form a logical network, called VP network (VPN), over the underlying physical network. VPN allows flexible management of network resources and hence its design is an important iss...
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Virtual paths (VPs) in an ATM network form a logical network, called VP network (VPN), over the underlying physical network. VPN allows flexible management of network resources and hence its design is an important issue in designing an ATM network. In this paper, we consider the VPN design problem which is formulated as an optimization problem with the objective of minimizing the switching and transmission cost, and control and management cost. We present here, a two-phase heuristic solution for designing a good VPN for a given traffic demand. The first phase is a routing phase in which a route is found between every node pair in the network. In the second phase, paths are selected as VPs using the set of routes generated in the routing phase. A path is selected as a VP so as to minimize the following parameters: (i) the total number of VPs configured;(ii) the number of VPs carried by a link (load);and (iii) the VP hopcount, the number of VPs that are concatenated to form a virtual channel (VC). We study the performance of the proposed algorithm through extensive simulation on various networks. The results show that the VPN generated by the proposed algorithm is good in minimizing the number of VPs configured, the load on a link, and the VP hopcount. The comp.rison of the results obtained by the proposed algorithm and that of Ahn et al. shows that our algorithm performs better.
作者：
Im, Y.-T.Comp. Aided Mat. Proc. Laboratory
Department of Mechanical Engineering ME3227 Korea Adv. Inst. Sci. T. 373-1 Kusong-dong Yusong-gu Taejon 305-701 Korea Republic of
The evolution of modern technology demands ever-increasing international comp.titiveness of manufacturing processes and products, requiring less design and manufacturing costs. In order to achieve this goal the design...
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The evolution of modern technology demands ever-increasing international comp.titiveness of manufacturing processes and products, requiring less design and manufacturing costs. In order to achieve this goal the design and manufacturing engineers work together as a team to come up with an economical solution meeting given constraints. As a first-step solution, new materials and processes or technologies to be applied will be sought with the help from a comp.ter-aided-design system that is based on either artificial intelligence techniques or numerical simulation tools. Some issues involved with this approach in developing forming processes of multi-stage forming, bar rolling, rolling, injection molding, and comp.ession molding, are discussed in this paper.
This paper presents a new application of spin-on glass to fabricate nonplanar dielectric structures (channel plate microstructures) with aspect ratios (i.e., ratio of channel length to channel width) of 20:1. A variet...
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This paper presents a new application of spin-on glass to fabricate nonplanar dielectric structures (channel plate microstructures) with aspect ratios (i.e., ratio of channel length to channel width) of 20:1. A variety of microchannel geometries have been fabricated. The LIGA process is used to make nickel molds up to 150 μm in height with mechanically planarized surfaces. Spin-on glass (SOG) is applied to obtain glass structures in nickel molds. A multiple dispensing/drying/curing process was developed resulting in crack-free SOG structures. Reverse electroplating is used to remove the nickel mold and release the glass structures. The resulting freestanding glass microchannel plates (>100 μm in height) demonstrated good electrical properties (400-V/μm breakdown voltage) and good spatial definition.
The reliability of a distributed comp.ting system depends on the reliability of its communication links and nodes and on the distribution of its resources, such as programs and data files. Many algorithms have been pr...
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The reliability of a distributed comp.ting system depends on the reliability of its communication links and nodes and on the distribution of its resources, such as programs and data files. Many algorithms have been proposed for comp.ting the reliability of distributed comp.ting systems, but they have been applied mostly to distributed comp.ting systems with perfect nodes. However, in real problems, nodes as well as links may fail. This paper proposes two new algorithms for comp.ting the reliability of a distributed comp.ting system with imperfect nodes. Algorithm I is based on a symbolic approach that includes two passes of comp.tation. Algorithm II employs a general factoring technique on both nodes and edges. comp.risons with existing methods show the usefulness of the proposed algorithms for comp.ting the reliability of large distributed comp.ting systems.
In shape rolling, the determination of roll pass and profile design is of importance. In the present investigation, a knowledge-based expert system is developed for the design of roll pass and profile sequences for th...
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In shape rolling, the determination of roll pass and profile design is of importance. In the present investigation, a knowledge-based expert system is developed for the design of roll pass and profile sequences for the shape rolling of round and square bars. For development of the program, C++ language and an object oriented programming technique were utilized in consideration of the flexibility and expandability of the program. A backward chaining algorithm was employed for the inference engine to determine the manufacturing sequences in reverse order based on design rules extracted from the literature. For optimization of the process sequence design, the number of roll passes was minimized by comp.ring the error between the inferred roll passes and the initial error provided as input. In the currently developed expert system, five geometries such as box, square, diamond, oval and round were introduced as a basic geometry to describe the intermediate roll geometries. In addition, the roll separating force, area reduction and change of length at each stage of shape rolling were determined and displayed on the monitor of a personal comp.ter. The system was applied for the shape rolling of round and square bars. The process sequences determined were proven to be reasonable comp.red to those available at practice.
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