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检索条件"机构=Institut Telecom/Telecom-ParisTech - Departement ComElec"

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Fault attacks on projective-to-affine coordinates conversion

引用

4th Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2013

作者： Maimuţ, Diana Murdica, Cédric Naccache, David Tibouchi, Mehdi Département d'Informatique École Normale Supérieure 45 rue d'Ulm F-75230 Paris Cedex 05 France Secure-IC S.A.S. 80 avenue des Buttes de Coësmes F-35700 Rennes France Département COMELEC Institut TELECOM TELECOM ParisTech CNRS LTCI Paris France Okamoto Research Laboratory NTT Secure Platform Laboratories 3-9-11 Midori-cho Musashino-shi Tokyo JP-180-8585 Japan

ISBN: (纸本)9783642400254

This paper presents a new type of fault attacks on elliptic curves cryptosystems. At EUROCRYPT 2004, Naccache et alii showed that when the result of an elliptic curve scalar multiplication [k] P (computed using a fixed scalar multiplication algorithm, such as double-and-add) is given in projective coordinates, an attacker can recover information on k. The attack is somewhat theoretical, because elliptic curve cryptosystems implementations usually convert scalar multiplication's result back to affine coordinates before outputting [k]P. This paper explains how injecting faults in the final projective-to-affine coordinate conversion enables an attacker to retrieve the projective coordinates of [k]P, making Naccache et alii's attack also applicable to implementations that output points in affine coordinates. As a result, such faults allow the recovery of information about k. © 2013 Springer-Verlag Berlin Heidelberg.

关键词： Geometry

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Compact patch antenna for Automatic Identification System (AIS)

Compact patch antenna for Automatic Identification System (A...

引用

2012 15th International Symposium on Antenna Technology and Applied Electromagnetics, ANTEM 2012

作者： Dousset, Thierry Renard, Christian Diez, Hubert Sarrazin, Julien Lepage, Anne Claire Department: RWS-IM/RF-AA Elancourt France Department: DCT/RF/AN Toulouse France Institut Mines-Telecom Telecom ParisTech Department: Comelec Paris 13ème France

This paper presents a radiating element developed for the space AIS application. This element is a compact sized and reduced mass microstrip patch antenna integrating frequency resonant adjustment devices. Theoretical... 详细信息

ISBN: (纸本)9781467302913

关键词： Microstrip antennas

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A Small and High-Performance Coprocessor for Fingerprint Match-on-Card

A Small and High-Performance Coprocessor for Fingerprint Mat...

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Euromicro Symposium on Digital System Design

作者： Taoufik Chouta Jean-Luc Danger Laurent Sauvage Tarik Graba CNRS LTCI Département COMELEC Institut TELECOM TELECOM ParisTech Paris France

In this paper we put forward a high-performance biometric fingerprint authentication algorithm for Match-On-Card (MOC) applications, compatible with the INCITS 378 and ISO/IEC 19794 standard. An efficient hardware implementation is proposed to adapt the algorithm for constrained embedded systems as smart cards. Time and memory complexities are reduced such that both integration and real time matching-on card can be met. The proposed architecture drops the required memory to 0.05% w.r.t. initial complexity, without any performance degradation. Therefore, the proposed solution is sufficient to meet the high level of security and the low computation time required in demanding authentication systems (e.g airports, electronic commerce and banking transactions).

关键词： Smart cards Standards Memory management Histograms Skin Feature extraction Arrays

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System-level methods to prevent reverse-engineering, cloning, and Trojan insertion

System-level methods to prevent reverse-engineering, cloning...

引用

6th International Conference on Information Systems, Management and Technology, ICISTM 2012

作者： Guilley, Sylvain Danger, Jean-Luc Nguyen, Robert Nguyen, Philippe Telecom.-ParisTech. COMELEC Departement CNRS LTCI UMR 5141 46 rue Barrault Paris 75 013 France Secure-IC S.A.S. 80 avenue des Buttes de Coësmes 35 700 Rennes France

ISBN: (纸本)9783642291654

The reverse-engineering (RE) is a real threat on high-value circuits. Many unitary solutions have been proposed to make RE difficult. Most of them are low-level, and thus costly to design and to implement. In this paper, we investigate alternative solutions that attempt to deny the possibility of RE using high-level methods, at virtually no added cost. © 2012 Springer-Verlag.

关键词： Cloning

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From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications

From Cryptography to Hardware: Analyzing Embedded Xilinx BRA...

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Annual IEEE/ACM International Symposium on Microarchitecture Workshops (MICROW)

作者： Shivam Bhasin Sylvain Guilley Jean-Luc Danger CNRS LTCI Laboratoire Traitement et Communication de lInformation (UMR 5141) Institut MINES-TELECOM Department COMELEC TELECOM ParisTech Paris France

Design of cryptographic applications need special care. For instance, physical attacks like Side-Channel Analysis (SCA) are able to recover the secret key, just by observing the activity of the computation, even for mathematically robust algorithms like AES. SCA considers the "leakage" of a well chosen intermediate variable correlated with the secret. Field programmable gate-arrays (FPGA) are often used for hardware implementations for low to medium volume productions or when flexibility is needed. They offer many possibilities for the computation, like small Look-Up Tables (LUT) and embedded block memories (BRAM). Certain countermeasures can be deployed, like dual-rail logic or masking, to resist SCA on FPGA. However to design an effective countermeasure, it is of prime importance for a designer to know the main leakage sources of the device. In this article, we analyze the leakage source of a Xilinx Virtex V FPGA by studying 3 different AES architectures. The analysis is based on real measurements by using specific leakage models of the sensitive variable, adapted to each architecture. Our results demonstrate that, BRAM which were considered to leak less traditionally, are found to be equally vulnerable if we change the attack target from address register to output latch. Hence by providing important clues about the leakage, this study allows the designers to enhance the robustness of their implementation in FPGA.

关键词： Field programmable gate arrays Registers Table lookup Cryptography Latches Clocks

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A 0.6 -3.6 GHz CMOS Wideband Demodulator for 4G Mobile Handsets

A 0.6 -3.6 GHz CMOS Wideband Demodulator for 4G Mobile Hands...

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European Microwave Integrated Circuits Conference

作者： Antoine Khy Bernard Huyart Departement d'Electronique et Communications (COMELEC) TELECOM ParisTech

ISBN: (纸本)9781467323024

This paper presents a 0.6 - 3.6 GHz CMOS wideband demodulator dedicated to 4G Long Term Evolution - Advanced (LTE-A) mobile handsets. The circuit uses three paths 120° phase shifted from one another instead of only two 90° phase shifted I and Q paths, which is the conventional configuration encountered in the well-known in-phase/quadrature (I/Q) demodulator. Thus, the proposed architecture is less sensitive to phase mismatch and has therefore strong potential for wideband operation that will be mandatory in future LTE-A systems. Furthermore, an analog circuit integrated on-chip converts the three output paths to two, in order to be compatible with a conventional I/Q front-end architecture. The circuit was designed using the 0.13μm HCMOS9GP process provided by ST Microelectronics. The chip size is 1.79mm × 1.3mm and it consumes 11.5 mW. This very high bandwidth (over 140%) demodulator which is compliant with integration in LTE-A mobile handsets is to our knowledge one of the very few dealing with this topic.

关键词： 4G CMOS Demodulation LTE-Advanced Mobile handsets RF front-ends Wireless wideband communications Zero IF receivers

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Compact patch antenna for Automatic Identification System (AIS)

Compact patch antenna for Automatic Identification System (A...

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International Symposium on Antenna Technology and Applied Electromagnetics and the Canadian Radio Science Meeting, ANTEM/URSI

作者： Thierry Dousset Christian Renard Hubert Diez Julien Sarrazin Anne Claire Lepage Department: RWS-IM/RF-AA Thales Systèmes Aéroportés Elancourt France Department: DCT/RF/AN Centre National d'Etudes Spatiales Toulouse France Institut Mines-Telecom LTCI Department: Comelec Telecom ParisTech Paris France

关键词： Frequency measurement Dispersion Bandwidth Couplings

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Formal security evaluation of hardware Boolean masking against second-order attacks

Formal security evaluation of hardware Boolean masking again...

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IEEE International Symposium on Hardware-Oriented Security and Trust

作者： Maghrebi, Houssem Guilley, Sylvain Danger, Jean-Luc Département COMELEC Institut TELECOM TELECOM ParisTech 46 rue Barrault 75 634 Paris Cedex France

ISBN: (纸本)9781457710575

The masking countermeasure in hardware has been widely studied, for its simplicity and its efficiency. Notably, no care is required at backend level and the throughput is not affected with respect to an unprotected implementation. In this article, we are concerned with a formal security evaluation of Boolean hardware masking schemes. Following a practice-oriented evaluation framework introduced at EURO-CRYPT'2009 [22], we compute both leakage and attack metrics. The hardware implementations have the specificity that the signal to noise ratio is below 1. In this particular case, we prove that a leakage metric (namely the mutual information) allows to characterize perfectly the best attack. This was previously unknown;moreover, we exhibit explicitly the links between leakage and attacks metrics. This result is in line with [10] but conflicts with [24]. More precisely, second-order DPA with a centered product combination function yields the largest leaks and the most powerful attacks. However, those are not possible if the implementation is "zero-offset", an implementation of first-order masking only possible in hardware. Furthermore, even the sub-optimal attacks are impeded, due to the high noise that characterizes parallel hardware crypto-processors. Therefore, masked implementations in hardware reach much higher security levels than software counterparts while not degrading significantly the computation throughput. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques

Enhancement of simple electro-magnetic attacks by pre-charac...

引用

作者： Meynard, Olivier Réal, Denis Flament, Florent Guilley, Sylvain Homma, Naofumi Danger, Jean-Luc Département COMELEC Institut TELECOM TELECOM ParisTech Paris France DGA Information Superiority Bruz France Graduate School of Information Sciences Tohoku University Japan

ISBN: (纸本)9783981080179

SPA/SEMA (Simple Power/Electro-magnetic Analysis) attacks performed on public-key cryptographic modules implemented on FPGA platforms are well known from the theoretical point of view. However, the practical aspect is not often developed in the literature. But researchers know that these attacks do not always work, like in the case of an RSA accelerator. Indeed, SEMA on RSA needs to make a difference between square and multiply which use the same logic;this contrast with SEMA on ECC, which is easier since doubling and add that are two different operations from the hardware point of view. In this paper, we wonder what to do if a SEMA fails to succeed on a device. Does it mean that no attack is possible? We show that hardware demodulation techniques allow the recording of a signal with more information on the leakage than a raw recording. Then, we propose a generic and fast method enabling to find out demodulation frequencies. The effectiveness of our methods is demonstrated through actual experiments using an RSA processor on the SASEBO FPGA board. We show cases where only demodulated signals permit to defeat RSA. © 2011 EDAA.

关键词： Demodulation

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Formal security evaluation of hardware Boolean masking against second-order attacks

Formal security evaluation of hardware Boolean masking again...

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IEEE International Workshop on Hardware-Oriented Security and Trust (HOST)

作者： Houssem Maghrebi Sylvain Guilley Jean-Luc Danger Département COMELEC Institut TELECOM CNRS LTCI (UMR 5141) TELECOM ParisTech Paris France

The masking countermeasure in hardware has been widely studied, for its simplicity and its efficiency. Notably, no care is required at backend level and the throughput is not affected with respect to an unprotected implementation. In this article, we are concerned with a formal security evaluation of Boolean hardware masking schemes. Following a practice-oriented evaluation framework introduced at EURO-CRYPT'2009, we compute both leakage and attack metrics. The hardware implementations have the specificity that the signal to noise ratio is below 1. In this particular case, we prove that a leakage metric (namely the mutual information) allows to characterize perfectly the best attack. This was previously unknown; moreover, we exhibit explicitly the links between leakage and attacks metrics. This result is in line with but conflicts with. More precisely, second-order DPA with a centered product combination function yields the largest leaks and the most powerful attacks. However, those are not possible if the implementation is “zero-offset”, an implementation of first-order masking only possible in hardware. Furthermore, even the sub-optimal attacks are impeded, due to the high noise that characterizes parallel hardware crypto-processors. Therefore, masked implementations in hardware reach much higher security levels than software counterparts while not degrading significantly the computation throughput.

关键词： Hardware Security Measurement Signal to noise ratio Software Mutual information

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