This paper focuses on reducing the power consumption of wireless microsensor networks. Therefore, a communication protocol named LEACH (low-energy adaptive clustering hierarchy) is modified. We extend LEACH's stoc...
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This paper focuses on reducing the power consumption of wireless microsensor networks. Therefore, a communication protocol named LEACH (low-energy adaptive clustering hierarchy) is modified. We extend LEACH's stochastic cluster-head selection algorithm by a deterministic component. Depending on the network configuration an increase of network lifetime by about 30% can be accomplished. Furthermore, we present a new approach to define lifetime of microsensor networks using three new metrics FND (First Node Dies), HNA (Half of the Nodes Alive), and LND (Last Node Dies).
True single phase clock logic techniques, e.g. with alternating arranged Nand P-logic cells, yield easily to design circuits with standard cells and high speed potential. The disadvantages are a difficult clock tree d...
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In this paper we present a scheduling coprocessor device for uniprocessor computer systems running a real-time operating system (RTOS). The coprocessor shortens the scheduling time of the operating system by performin...
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Scheduling time impact on system performance increases especially when using dynamic priority algorithms, because of the enlarged computational effort at runtime. This overhead can be reduced by using dedicated hardwa...
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Scheduling time impact on system performance increases especially when using dynamic priority algorithms, because of the enlarged computational effort at runtime. This overhead can be reduced by using dedicated hardware that does the time consuming computations necessary for scheduling. This can be a coprocessor capable of implementing dynamic scheduling algorithms which are, until now, rarely used because of their complex computations at schedule time. One of these algorithms is Least-Laxity-First (LLF). This is an optimal scheduling methodology that allows detection of time constraint violations ahead of reaching a task's deadline, but has the disadvantage of showing poor runtime behavior in some special situations ("thrashing"). In this paper, we present a universal deterministic scheduling coprocessor that implements the newly developed Enhanced Least-Laxity-First-algorithm (ELLF) which eliminates this disadvantage of LLF. Computation time of this device is rather a matter of time resolution than of the number of tasks.
In 1996, about 600 million IC cards were manufactured worldwide. Due to very small die sizes (max. 25 mm/sup 2/) smartcards encounter more severe restrictions than conventional coprocessors. We study coprocessor archi...
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In 1996, about 600 million IC cards were manufactured worldwide. Due to very small die sizes (max. 25 mm/sup 2/) smartcards encounter more severe restrictions than conventional coprocessors. We study coprocessor architectures for very fast but area efficient modular exponentiation (FME) based on Montgomery multiplication. For assessment purposes we developed an evaluation board containing a 8051 microprocessor, a XILINX FPGA and RAM with variable bus width (8b to 32b). We evaluated these architectures in terms of the main design parameters to ease design decisions for smartcards in arbitrary technologies.
The CORDIC algorithm is used in many fields of signal processing for computation of elementary functions. Its main advantages are versatility and simplicity. When implemented in a word parallel pipeline it yields the ...
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The CORDIC algorithm is used in many fields of signal processing for computation of elementary functions. Its main advantages are versatility and simplicity. When implemented in a word parallel pipeline it yields the highest possible throughput. However this solution is accompanied with increased hardware complexity and chip area requirements. The goal of this paper is to develop redundant CORDIC pipeline architectures yielding very low chip area. The speed does not decrease at all when compared with other proposals. Our novel architectures result in the smallest redundant CORDIC implementation known to the authors. It also exhibits considerably less gate switching activity thus also reducing power consumption.
We are involved in the design and control of a 1-dimensional positioning mechanism for a range of 50 /spl mu/m and an accuracy of 30 pm. Only piezoelectric actuators can be used to manage such small displacements. How...
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ISBN:
(纸本)0780341872
We are involved in the design and control of a 1-dimensional positioning mechanism for a range of 50 /spl mu/m and an accuracy of 30 pm. Only piezoelectric actuators can be used to manage such small displacements. However, these actuators show hysteretic behavior and lengthening saturation. The extremely small displacements are measured by means of capacitive sensors. In order to design a controller a model of the positioning mechanism and the actuators is developed. Contrary to the existing literature, in our model the hysteresis is described by a differential equation. The mechanical characteristics of the design, and therefore also of the model, are chosen such that they are practically realizable and advantageous for controller design. The final nonlinear fifth order state space model is believed to be suitable for a nonlinear control technique like feedback linearization.
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