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Attacking a Joint Protection Scheme for Deep Neural Network Hardware Accelerators and Models

Attacking a Joint Protection Scheme for Deep Neural Network ...

引用

IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)

作者： Simon Wilhelmstätter Joschua Conrad Devanshi Upadhyaya Ilia Polian Maurits Ortmanns Institute of Microelectronics University of Ulm Ulm Germany Institute for Computer Architecture and Computer Engingeering University of Stuttgart Stuttgart Germany

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

The tremendous success of artificial neural networks (NNs) in recent years, paired with the leap of embedded, low-power devices (e.g. IoT, wearables and smart sensors), gave rise to specialized NN accelerators that enable the inference of NNs in power-constrained environments. However, manufacturing or operating such accelerators in un-trusted environments poses risks of undesired model theft and hardware counterfeiting. One way to protect NN hardware against those threats is by locking both the model and the accelerator with secret keys that can only be supplied by entitled authorities (e.g. chip designer or distributor). However, current locking mechanisms contain severe drawbacks, such as required model retraining and vulnerability to the powerful satisfyability checking (SAT)-***, an approach for jointly protecting the model and the accelerator was proposed. Compared to previous locking mechanisms, it promises to avoid model retraining, not leak useful model information, and resist the SAT-attack, thereby securing the NN accelerator against counterfeiting and the model against intellectual property infringement. In this paper, those claims are thoroughly evaluated and severe issues in the technical evidence are identified. Furthermore, an attack is developed that does not require an expanded threat model but is still able to completely circumvent all of the proposed protection schemes. It allows to reconstruct all NN model parameters (i.e. model theft) and enables hardware counterfeiting.

关键词： Threat modeling Artificial neural networks Resists Robustness Manufacturing Security Protection

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Enabling Power Side-Channel Attack Simulation on Mixed-Signal Neural Network Accelerators

Enabling Power Side-Channel Attack Simulation on Mixed-Signa...

引用

Omni-layer Intelligent Systems (COINS), International Conference on

ISBN: (数字)9798350349597

ISBN: (纸本)9798350349603

Due to the tremendous success of Deep Learning with neural networks (NNs) in recent years and the simultaneous leap of embedded, low-power devices (e.g. wearables, smart-phones, IoT, and smart sensors), enabling the inference of those NNs in power-constrained environments gave rise to specialized NN accelerators. One paradigm followed by many of those accelerators was the transition from digital domain computing towards performing operations in the analog domain, turning them from digital to mixed-signal NN accelerators. While power-efficiency and inference accuracy have been researched with increasing interest, security and protection against a side-channel attack (SCA) have not found much attention. However, side-channels pose a major security concern by allowing an attacker to steal valuable knowledge about proprietary NNs deployed on accelerators. In order to evaluate mixed-signal NNs accelerators concerning SCA robustness, its tendency to leak information through the side-channel needs investigation. In this work, we propose a methodology for enabling side-channel analysis of mixed-signal NNs accelerators, which shows reasonable accuracy in an early development stage. The approach enables the reuse of large portions of design sources for simulation and production while providing flexibility and fast development cycles for changes to the analog design.

关键词： Accuracy Computational modeling Artificial neural networks Side-channel attacks Production Turning Robustness

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