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16th International Conference on computer Graphics, Visualization, computer Vision and Image Processing, CGVCVIP 2022, 8th International Conference on Connected Smart Cities, CSC 2022, 7th International Conference on Big Data Analytics, Data Mining and Computational Intelligence, BigDaCI 2022, and 11th International Conference on Theory and Practice in Modern Computing, TPMC 2022 - Held at the 16th Multi Conference on computer Science and Information systems, MCCSIS 2022

作者： Khattar, Joseph Hahn, Eike Telawi, Samer Schwarz, Michael Boercsoek, Josef ICAS Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

ISBN: (纸本)9789898704429

Recent advancements in the embedded systems field have resulted in more complicated systems with application-specific blocks (IP cores), often known as system on Chip (SoC) devices. Several redundancy-based embedded designs provide reliability and safety for SoC in aeronautics, automotive, industrial automation, railway, and space. In this paper, a Safety system-on-Chip heterogenous1oo2 architecture is presented. The design is based on two open-source and proven in-use cores, LEON3 from Cobham Gaisler and RISCV processors SweRV EH1 from Western Digital. The SoC is implemented on a Xilinx FPGA system and supplemented with conventional peripherals from the Xilinx IP library and Cobham Gaisler. A software comparator is included for a diagnostic. Each core has independent IPs, and the software comparator evaluates data from both cores;in case of deviation, the system is rendered to an energized safe state. © MCCSIS *** rights reserved.

关键词： system-on-chip

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RISC-V Based Safety system-on-Chip with Hardware Comparator 11

RISC-V Based Safety System-on-Chip with Hardware Comparator

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11th International Conference on Electronics, Communications and Networks, CECNet 2021

作者： Hahn, Eike Kalinowski, Dominik Mueller, Waldemar Abdelawwad, Mohamed Boercsoek, Josef ICAS Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

ISBN: (纸本)9781643682402

In this paper, a Safety system-on-Chip based on the open-source RISC-V processor SweRV EH1 from Western Digital is presented. A hardware comparator concept is followed. The SSoC is implemented on a Xilinx FPGA system and extended with standard peripherals from the Xilinx IP library and from Cobham Gaisler, so that the overall system has an Ethernet interface in addition to GPIO and UART. The goal is to create a complete redundancy approach with a hardware fault tolerance of nearly 1 from input to output based on the freely available RISC-V instruction set and prove its feasibility. © 2022 The authors and IOS Press.

关键词： system-on-chip

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Efficiency Measurement of Compressed Air Compressors Using High Availability SoC with 1oo2 Redundancy architecture 11

Efficiency Measurement of Compressed Air Compressors Using H...

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11th International Conference on Electronics, Communications and Networks, CECNet 2021

作者： Abdelawwad, Mohamed Hahn, Eike Boercsoek, Josef Fairbrother, Julian Al Shahadat, Tarek Otto, Peter ICAS Institute for Computer Architecture and System Programming University of Kassel Kassel Germany Postberg + Co. GmbH Kassel Germany

ISBN: (纸本)9781643682402

Compressed air systems are essential components in various industrial and everyday applications. The efficiency of these systems is very important due to their role in the energy consumption of industrial plants. To increase efficiency, a new concept for compressed air compressors based on Industry 4.0 is presented. Due to the aggressive environmental conditions in which the compressed air compressors operate, a new design of a SoC with high availability based on 1oo2 redundancy architecture is developed. © 2022 The authors and IOS Press.

关键词： Energy utilization

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Towards safe data flow processing by integration of design by contract in deterministic UML activities

Towards safe data flow processing by integration of design b...

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2011 23rd International Symposium on Information, Communication and Automation Technologies, ICAT 2011

作者： Daw, Zamira Vetter, Marcus Boercsoek, Josef Institute of Embedded Systems Hochschule Mannheim - University of Applied Sciences Mannheim Germany Dept. of Computer Architecture and System Programming University of Kassel Kassel Germany

ISBN: (纸本)9781457707469

Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For safety related applications, this pipeline has to be able to identify and react to failures. The DMOSES model-driven development method uses deterministic UML activities to describe and implement data flow processing. This method ensures deterministic behavior of concurrent processing. Design by Contract defines formal, precise and verifiable interfaces for software components. We propose a development method for safe data flow processing based on the integration of this concept in deterministic UML activities. This integration allows the identification of errors by detection of contracts violation. This paper presents an extension of the DMOSES tool for contracts verification at the model level and their monitoring at runtime. © 2011 IEEE.

关键词： Pipelines

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Safe position detection based on safety system-on-chip (SSOC) for wireless IoT application

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International Journal of Circuits, systems and Signal Processing 2020年 14卷 1040-1046页

作者： Börcsök, Josef Hafiz, Muhammad Ikram Alsuleiman, Ahmed Schwarz, Michael Abdelawwad, Mohamed ICAS Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

— Cyber Physical systems (CPS) are predestined for use in Industry 4.0 applications. However, the interaction between the virtual and physical world also creates risks that is essential to be controlled. In highly automated industrial systems, for example, robots are used in confined spaces together with working humans. The risk posed by such systems endangers, among others, the people working there. This paper presents an approach to ensure the safety of the situation described above, which makes the workspace of industrial robots safer by implementing a safe workspace detection system. This system comprises several detection sensors implemented in a 2oo3 safety architecture and a Safety system on a Chip (SSoC) based on a safe 1oo2 system architecture. The safety-related redundancy provided by the detection and calculation elements enables a safe position detection of the robotic arm in the 3-dimensional space. The presented system monitors the position of the robotic arm and thus supports the safety of the surrounding objects and the people working there by leading to a safe standstill or to a reduced speed of movement of the robot as soon as the defined and permitted working space is left. © 2020, North Atlantic University Union NAUN. All rights reserved.

关键词： system theory

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Concept of an Optical Distance and Speed Sensor Using Novel Offsetless Spatial Frequency Filters in the Area of Functional Safety 32

Concept of an Optical Distance and Speed Sensor Using Novel ...

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32nd IEEE International Symposium on Industrial Electronics, ISIE 2023

作者： Wasinski, Frank Bonath, Werner Ricklefs, Ubbo Borcsok, Josef Schwarz, Michael Hahn, Eike University of Applied Sciences THM Dept. of Electrical Engineering and Information Technology Giessen Germany Institute for Computer Architecture and System Programming University of Kassel ICAS Kassel Germany

ISBN: (纸本)9798350399714

Optical speed sensors based on the spatial frequency filter method are a proven technology that offer high measurement accuracy over a wide speed range. Newly developed variants also enable measurements at very low speeds and increase the robustness of the method [1]. This makes the sensor very suitable for use in the area of functional safety. A measurement chain up to safety integrity level 3 (SIL3) should be feasible via a combination with a safety system on a chip (SoC) for evaluating the measurement data and an extension of the sensor module to include safety-related elements [2], [3]. By integrating the sensor at IC level, a compact overall solution is to be made possible. After the first successful tests with the safety SoC, further examinations of the measuring method with regard to functional safety are now necessary. © 2023 IEEE.

关键词： system-on-chip

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A Practical Approach for Reliability Prediction of Safety Critical Software Using Multi-Model Ensemble Techniques 7

A Practical Approach for Reliability Prediction of Safety Cr...

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7th International Conference on system Reliability and Safety, ICSRS 2023

作者： Ouertani, Aymen Krini, Ossmane Börcsök, Habil. Josef Institute of Functional Safety & Cyber Security Baden-Wuerttemberg Cooperative State University Lörrach Germany Computer Architecture und System Programming University of Kassel Kassel Germany

ISBN: (纸本)9798350306057

This paper introduces a novel and comprehensive approach for estimating the reliability of safety critical software components in autonomous vehicle motion systems. The proposed approach in this paper presents a combination software reliability model (CSRM) that integrates multiple non-homogeneous Poisson process (NHPP) software reliability growth models (SRGMs) to achieve a reasonable compromise between accuracy, the trade-off between the goodness of fit and the simplicity, and stability. By using machine learning techniques, the CSRM effectively combines the strengths of individual SRGMs while mitigating their weaknesses through suitable evaluation and calibration techniques. The developed CSRM has been successfully applied and validated to facilitate a smoother and more efficient evaluation of reliability targets for software components in autonomous robotic wheelchair (ARW). Based on the validation results, the new CSRM has significantly enhanced the efficiency of the process for evaluating whether the defined reliability goals were being achieved. Furthermore, has facilitated a more accurate assessment of the need for further test executions and better planning of the required verification and validation session. This new approach provides valuable insights into the reliability of the developed software, particularly for software developers lacking extensive experience in identifying and applying appropriate SGRM. © 2023 IEEE.

关键词： Economic and social effects

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The benefits of middleware for safety-related systems-on-chip

The benefits of middleware for safety-related systems-on-chi...

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International Symposium on Fundamentals of Electrical Engineering (ISFEE)

作者： Karolin Löser Emil Delic Michael Schreiber Ali Hayek Josef Börcsök Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

system-on-Chip architectures are increasingly designed for safety-related purposes. As a very high level of interlocking of hard- and software is required for such specialized systems, different concepts for the software composition are necessary. This paper investigates the benefits resulting from the utilization of a middleware which handles all low-level hardware access demanded by the application. Several measures recommended by standard IEC 61508 are implemented “quasi-automatically” if a certified middleware is used. In addition, the certification effort is drastically decreased if the implementation of main functionalities is based on certified, reused components. Another “side-effect” is the hiding of details concerning the system-on-chip and the operating system as the application always uses the middleware interfaces.

关键词： system-on-chip IEC standards Hardware Middleware Safety

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CAN open safety on safety-related system-on-chip

CAN open safety on safety-related system-on-chip

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XXII International Symposium on Information, Communication and Automation Technologies, ICAT

作者： Hamid Rahmani Karolin Löser Richard Thum Ali Hayek Josef Börcsök Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

Although the traditional task of communication protocols is the transmission of data, this is actually not completely sufficient if it is used in safety sectors. Therefore, it must be enhanced. In order to detect and overcome failures in systems, risk analysis and failure measurement must be taken into account in each safety-related system. This paper describes the advantages of having a safety-related system-on-chip with on-chip diagnostics in order to develop a safe transmission protocol. Here the concept of a CANopen Safety protocol stack on top of a safety-related system-on-chip that yields reliability to the complete product is presented.

关键词： Decision support systems

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Validation of a SIL3 middleware for safety-related system-on-chips

Validation of a SIL3 middleware for safety-related system-on...

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Proceedings of the International Convention MIPRO

作者： Emil Delic Michael Schreiber Ali Hayek Josef Börcsök Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

The aim is reducing IEC 61508 certification effort for safety-related applications. Therefore, an object-oriented middleware has been implemented which, once being SIL3-certified, would allow transferring safety-related aspects from the application into an already-certified code layer. Safety-related applications using this middleware then could be written as straightforward as non-safety-related code. The SIL3 middleware is designed for an 8051-based microcontroller. Because of the 8-bit CPU architecture, several limitations have been encountered. These issues are explained in this paper, and solutions are proposed. The middleware will be used on the multi-more safety chip. SIL3 certified multi-core architecture for safety-related applications is described. Also, the SIL3 middleware architecture is given. The middleware is modular. Therefore, if the user does not want to use some modules they will not be included and code footprint will be smaller. In the SIL3 middleware numerous design patterns can be found. Patterns description and purpose are explained. The pseudo code for the singleton pattern is shown. Moreover, module implementation is depicted. The validation of the middleware is presented and the V-model for the middleware is provided. It conforms to the IEC 61508.

关键词： Middleware IEC standards Safety system-on-chip computer architecture Certification

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