Due to the complexity of microprocessor, an efficient testing is a crucial point and serious challenge in safety systems. A new instruction opcode for ALU based Built-In-Test (BIT) is proposed in this paper. With this...
Due to the complexity of microprocessor, an efficient testing is a crucial point and serious challenge in safety systems. A new instruction opcode for ALU based Built-In-Test (BIT) is proposed in this paper. With this novel method stuck-at-fault in Multiplexer (MUX) for Arithmetic Logic Unit (ALU) can be determined. A model that consists of the command and faulty states is developed. According to the designed state model, an algorithm and pseudo program that tests the stuck-at-fault in MUX is implemented and described in this paper.
In order to use electronic systems comprising of software and hardware components in safety related and high safety related applications, it is necessary to meet the Marginal risk numbers required by standards and leg...
In order to use electronic systems comprising of software and hardware components in safety related and high safety related applications, it is necessary to meet the Marginal risk numbers required by standards and legislative provisions. Existing processes and mathematical models are used to verify the risk numbers. On the hardware side, various accepted mathematical models, processes, and methods exist to provide the required proof. To this day, however, there are no closed models or mathematical procedures known that allow for a dependable prediction of software reliability. This work presents a method that makes a prognosis on the residual critical error number in software. Conventional models lack this ability and right now, there are no methods that forecast critical errors. The new method will show that an estimate of the residual error number of critical errors in software systems is possible by using a combination of prediction models, a ratio of critical errors, and the total error number. Subsequently, the critical expected value-function at any point in time can be derived from the new solution method, provided the detection rate has been calculated using an appropriate estimation method. Also, the presented method makes it possible to make an estimate on the critical failure rate. The approach is modelled on a real process and therefore describes two essential processes - detection and correction process.
In order to measure the effectiveness of safety protection systems there are several design parameters. Diagnostic coverage factor is one of the most important parameter which influences all architectures. In this sho...
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In order to measure the effectiveness of safety protection systems there are several design parameters. Diagnostic coverage factor is one of the most important parameter which influences all architectures. In this short paper the relationship between PFD avg , DC and T I are presented. 1oo2 and 1oo2D architectures are considered as examples.
In the standard IEC 61508 miscellaneous architectures for safety related systems are introduced. Depending on the required safety, reliability and availability levels several architectures such as 1002-, 2002-, 1003-,...
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With the publication and enforcement of the standard IEC 61508 of safety related systems, recent systemarchitectures have been presented and evaluated. Among a number of techniques and measures to the evaluation of s...
With the publication and enforcement of the standard IEC 61508 of safety related systems, recent systemarchitectures have been presented and evaluated. Among a number of techniques and measures to the evaluation of safety integrity level (SIL) for safety-related systems, several measures such as reliability block diagrams and Markov models are used to analyze the probability of failure on demand (PFD) and mean time to failure (MTTF) which conform to IEC 61508. The current paper deals with the quantitative analysis of the novel 1oo4-architecture (one out of four) presented in recent work. Therefore sophisticated calculations for the required parameters are introduced. The provided 1oo4-architecture represents an advanced safety architecture based on on-chip redundancy, which is 3-failure safe. This means that at least one of the four channels have to work correctly in order to trigger the safety function.
Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For...
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The paper is concerned with data transmission via channels composed of a memoryless binary symmetric channel and the erasure channel of Peter Elias. Channels of this type play an important role in modelling different ...
The paper is concerned with data transmission via channels composed of a memoryless binary symmetric channel and the erasure channel of Peter Elias. Channels of this type play an important role in modelling different types of networks especially wireless networks, and have been investigated using, amongst others, the theory of Markov chains. Channel Capacities and network flows have been determined. The authors focus their interest on some aspects of coding theory. They assume the data transmission to be protected by a linear code, a CRC for example, and determine the probability of undetected error of the code. They then consider redundant transmission via two or more channels with bit inversion, and calculate the probability of undetected error. They prove some inequalities that are useful instruments to estimate the rate of transmission errors and to determine safety integrity levels according to the standards. Finally the authors apply their results to Bluetooth channels suffering from different types of noise.
Software-Engineering is very important today. In industry (specifically by software critical system) it is important to produce high reliable software, i.e. software with low proportion of faults. To produce such reli...
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Software-Engineering is very important today. In industry (specifically by software critical system) it is important to produce high reliable software, i.e. software with low proportion of faults. To produce such reliable software, a long handling process is required, and because this process consumes a large amount of time and resources to achieve the desired reliability goals it is useful to use Software Reliability Stochastic Models to predict the required software testing time. In this paper a new approach to reflecting the residual number of critical failures in software-systems is introduced. There are currently very few processes enabling us to predict the reliability of the critical failures or the critical failure rate for critical systems. Furthermore, we will focus on distinguishing the critical failures in the software. We will thus distinguish both critical as well as non-critical failures in the Software. Therefore it is important to divide the process into two classes, detection- and correction class. To develop an approach it is necessary to determine corresponding distribution functions and model assumptions.
This paper presents a simulation environment, which is a C++/systemC based integrated framework for functional verification of designed components or electronic architectures and enhances the existing computer archite...
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This paper presents a simulation environment, which is a C++/systemC based integrated framework for functional verification of designed components or electronic architectures and enhances the existing computerarchitecture simulation tool named sefca. As the VHDL sources are converted to systemC it is sufficient for verification engineers to have a fundamental knowledge of C++ and the systemC library. The testbench framework uses the same graphical user interface (GUI) based on the wxPython library, which was presented in the sefca tool. Verification of the design is supported by the systemC verification library (SCV). Inter-Process-Communication is used to send the stimuli for simulation input from the GUI to the simulation process and the simulation results back to the online viewer in the GUI. With these enhancements sefca becomes a universal tool for testing the software and the hardware part of a new design at the same time. Working on the transaction level model (TLM) the proposed methodology offers a high performance and a high level of abstraction.
In the standard IEC 61508 miscellaneous architectures for safety related systems are introduced. Depending on the required safety, reliability and availability levels several architectures such as 1oo2-, 2oo2-, 1oo3-,...
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In the standard IEC 61508 miscellaneous architectures for safety related systems are introduced. Depending on the required safety, reliability and availability levels several architectures such as 1oo2-, 2oo2-, 1oo3-, and 2oo3-architectures can be selected. In this paper, the concept and calculation of a novel architecture is presented. The 1oo4-architecture (one out of four) represents an advanced safety architecture, which is 3-failure safe. This means that at least one of the four channels have to work correctly in order to trigger the safety function. In order to classify the quality of the proposed architecture for safety related systems the PFD-value is calculated. Additionally, the Markov-model for a 1oo4-architecture is introduced and the MTTF-value for this architecture is calculated. The results are high safety and high reliability.
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