system-on-Chip architectures are increasingly designed for safety-related purposes. As a very high level of interlocking of hard- and software is required for such specialized systems, different concepts for the softw...
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system-on-Chip architectures are increasingly designed for safety-related purposes. As a very high level of interlocking of hard- and software is required for such specialized systems, different concepts for the software composition are necessary. This paper investigates the benefits resulting from the utilization of a middleware which handles all low-level hardware access demanded by the application. Several measures recommended by standard IEC 61508 are implemented “quasi-automatically” if a certified middleware is used. In addition, the certification effort is drastically decreased if the implementation of main functionalities is based on certified, reused components. Another “side-effect” is the hiding of details concerning the system-on-chip and the operating system as the application always uses the middleware interfaces.
Due to the continuing development of semiconductor structures, it can be allowed nowadays to integrate faster and more efficient systems into a very small area of silicon. In such system-on-chip, all individual compon...
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Due to the continuing development of semiconductor structures, it can be allowed nowadays to integrate faster and more efficient systems into a very small area of silicon. In such system-on-chip, all individual components of a target control system can be integrated into a single silicon die at lowest level, which in turn contributes in saving the substantial space and reduces power consumption and production costs. With the consideration of the miniaturization of safety-related systems into system-on-chips, where usually complete redundant architectures along with memories and interfaces are integrated into small silicon structures, many advantages can be taken into account. These advantages extend to all levels of the development cycle. In the present paper, a concept for on-chip safety systemarchitecture is presented briefly. Primarily, a qualitative evaluation and analysis of the presented architecture is explicitly focused and discussed. The evaluation and analysis is based on a comparison to a similar conventional discrete safety-related architecture.
With the release of the second edition of the standard IEC 61508 for functional safety of electrical, electronic and programmable electronic systems, a set of methodologies and implementation techniques was presented,...
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With the release of the second edition of the standard IEC 61508 for functional safety of electrical, electronic and programmable electronic systems, a set of methodologies and implementation techniques was presented, which allows the realization and certification of safety-related solutions with on-chip redundancy. In a broader context, the standard ISO 26262 offers similar methodologies for safety solutions for automotive applications. The main focus of the research work of our institute is laid on the development and certification of safety-chips according to the standard IEC 61508. Together with an industrial partner, we are developing chip-based safety-related solutions for several industrial applications. In the same context, several semiconductor manufacturers addressed the development of such solutions in the last years, mainly with the focus on automotive applications. The present paper provides an overview of existing and planned safety chip architectures. Furthermore, a cursory analysis of the presented safety-chips is carried out with respect to the standard IEC 61508. A deep qualitative and quantitative analysis require experiments and simulations which will be carried out in future work.
Since the advent of traditional random access memory (RAM) tests, such as Checkerboard, more sophisticated tests and fault models have evolved, taking the characteristics of memories into account. Thus, given a specif...
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Since the advent of traditional random access memory (RAM) tests, such as Checkerboard, more sophisticated tests and fault models have evolved, taking the characteristics of memories into account. Thus, given a specific type of memory, it would be straightforward to determine suitable state-of-the-art tests. However, the question our research focuses on is: “Which RAM tests do not need to be performed due to the safety architecture?” Even high-performance tests do require execution time. In the range of safety-related systems, diagnostics may consume most of the central processing unit (CPU) time, depending on the architecture. Therefore, this paper depicts how architectural characteristics can be taken into account to reasonably simplify specific RAM tests. This paper introduces our research on RAM tests in the range of safety-related systems. Therefore, key topics are introduced, first: comprehensively and starting from scratch, thus enabling anyone to follow our research. Second, an example is shown on how detecting stuck-at faults of address and data words, as demanded by IEC 61508 Ed.2.0, can be simplified by taking advantage of a 1oo2D safety architecture.
New Solutions of autonomous vehicles, which are traveling along a painted line on the floor, have been found. In many cases navigation along a painted line will not be accepted because the ground will not be suitable ...
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New Solutions of autonomous vehicles, which are traveling along a painted line on the floor, have been found. In many cases navigation along a painted line will not be accepted because the ground will not be suitable for a painted line. Environmental concerns prohibit putting anything in or on the ground. A free navigation system is necessary. The load and the size of these vehicles increase. Areas where they are found are expanding. It is undoubtedly true that a safety related position detection system with a strong sense of accuracy would be needed to establish such a secure communication. A system that operates with high accuracy and high reliability is introduced here.
This paper describes the implementation and integration process of a complete communication computersystem on the field programmable gate array (FPGA). After such a design is reached, safety measures are integrated t...
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This paper describes the implementation and integration process of a complete communication computersystem on the field programmable gate array (FPGA). After such a design is reached, safety measures are integrated to achieve a safety-related architecture. For this purpose a diagnostic unit will be implemented, consisting of hardware and software tests. Hardware tests are related to the control of the FPGA functionality. They are based on the integration of two existing methods to reach complete hardware test coverage. The software tests are used for a continuous testing of the whole system (this means testing the central processing unit, bus systems, peripherals and memory). Furthermore, a safety multiplexer is integrated with the task to turn off the current operating system (main system) and to turn on a redundant system when a failure is introduced via the diagnostic unit. The safety multiplexer has to give the permission to the redundant system to receive the outputs from the main system in a way that is free from faults. The microcontroller ColdFire is used as a basis, which provides numerous features for the control of various peripherals as well as the connection of various types of memory.
In this paper a complete safety controller on a single chip is introduced. The presented chip is a comprehensive solution that includes a certified application specific integrated circuit for safety-critical applicati...
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In this paper a complete safety controller on a single chip is introduced. The presented chip is a comprehensive solution that includes a certified application specific integrated circuit for safety-critical applications according to the safety standard IEC 61508, meeting the safety integrity level SIL3. Furthermore, a SIL3 operating system and a SIL3 middleware are also briefly presented in this paper. Based on the presented solution, the smallest certified safety controller represents an innovative product and allows system manufacturers to create safe solutions that are ready for certification.
Critical security systems for energy supply depends upon energy storage by batteries or the cable supply. “What if this self-sufficient must be supplied?” The main focus of the paper lies on construction and adaptat...
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Critical security systems for energy supply depends upon energy storage by batteries or the cable supply. “What if this self-sufficient must be supplied?” The main focus of the paper lies on construction and adaptation of an impulse coupling which generates a sufficient voltage to supply to a monitoring system by using rotational energy at lower rotational speed and thus making a system self-sufficient energy supply system. Another main focus lies in the optimization of the failure rate in a system because of mechanical components. In this research project the theoretical approaches are checked by a suitable parameter frame in a real system. A fault tree analysis (FTA) was pulled up for the evaluation of the failure rate, to show potential failures and to validate these, we carried out other simulations by means of the Finite elements method (FEM).
In this paper nl approach of an on-chip safety systemarchitecture conforming to the second edition of the standard IEC 61508 is presented. The presented chip considers on-chip redundancy with the presence of diagnost...
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In this paper nl approach of an on-chip safety systemarchitecture conforming to the second edition of the standard IEC 61508 is presented. The presented chip considers on-chip redundancy with the presence of diagnostic units and is designed to meet the highest possible safety integrity level for on-chip systems. The presented on-chip safety system consists of two redundant processor channels, each of which has a processor unit, data memory, program memory, communication interfaces, inputs and outputs. Furthermore, on-chip diagnosis- and monitoring units and a communication core are integrated. The safety-related implementation of the proposed architecture is introduced in this paper. This includes hardware and software implementation methodologies. Finally, a brief evaluation of the presented architecture is presented.
Nowadays, many considerable efforts are focused on the development of efficient and effective systems that increase the productivity of vehicles by controlling and manipulating the extraordinary states, such as slidin...
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Nowadays, many considerable efforts are focused on the development of efficient and effective systems that increase the productivity of vehicles by controlling and manipulating the extraordinary states, such as sliding and spinning, during the operational time. Those states play a central role in the performance of the vehicles described as an interaction among different mechanical parts regarding their life-time, their wear and tear, as well as the maintenance costs. In addition, these states ultimately affect the safety of target system and its environment. Therefore, the necessity of avoiding, controlling, or manipulating these states to lower their effects into a tolerable level has become the major driver for conducting the current research work. In this paper, a prototype for safety-related platform for detecting and controlling railway vehicles states by means of vibration capture is presented. Additionally, test procedures in order to collect the vibration data related to each state are presented; these tests were performed under the supervision of an industrial partner. Moreover, the recognized initial patterns of the vibration signals related to the studied states are also introduced.
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