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IEEE International SOC Conference

作者： Shuang Liu Martin Radetzki Chair of Embedded Systems Institute of Computer Architecture and Computer Engineering University of Stuttgart Stuttgart Germany

ISBN: (数字)9798350377569

ISBN: (纸本)9798350377576

Chiplet-based systems have become prominent in large systems-on-Chips (SoCs) as a means to mitigate increasing design costs. However, the integration of multiple chiplets introduces new challenges in the interconnection network, potentially leading to deadlocks. In this paper, we propose an Integer Linear Programming (ILP) based design approach to address this issue. Our method considers various design factors for deadlock-free routing, such as topology, latency, load balancing, path diversity, and fault tolerance, applicable to both general-purpose chiplets and application-specific chiplets. It facilitates the determination of optimal turn restrictions for general-purpose chiplets or constructs optimal deadlock-free routing paths for application-specific chiplets if the communication patterns are known. The results demonstrate the capability of the method to find optimal solutions under various design considerations.

关键词： Fault tolerance Network topology Chiplets Fault tolerant systems System recovery Integer linear programming Routing Load management Topology System-on-chip

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Synergistic Floorplanning and Routing Topology Co-design for Application-Specific NoC Synthesis

Synergistic Floorplanning and Routing Topology Co-design for...

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IEEE International Symposium on Embedded Multicore Socs (MCSoC)

作者： Shuang Liu Martin Radetzki Chair of Embedded Systems Institute of Computer Architecture and Computer Engineering University of Stuttgart Stuttgart Germany

ISBN: (数字)9798331530471

ISBN: (纸本)9798331530488

Network-on-Chip (NoC) offers a promising solution for on-chip communication in highly integrated System-on-Chips (SoCs). NoCs can be designed with either regular or application-specific network topologies. While regular topologies are easy to design, they are not ideal for systems with heterogeneous processing elements (PEs) that vary in size. The design of application-specific NoCs, however, involves several interrelated problems that impact each other. This work addresses the challenges in the synthesis of application-specific NoCs by proposing an Integer Linear Programming (ILP) framework. This framework enables the co-design of major problems, including floorplanning, routing topology generation, routing path construction, and application mapping. Although the ILP framework can be applied to each problem individually or in a stepwise manner, the co-design of these interconnected problems allows synthesis steps to interact, enabling designers to explore the entire design space. Using this framework, we have analyzed various design configurations in the synthesis of application-specific NoCs.

关键词： Network topology Multicore processing Fault tolerant systems Network-on-chip System recovery Integer linear programming Routing Linear programming Topology Wire

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Early Execution for Soft Error Detection

Early Execution for Soft Error Detection

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International Conference on VLSI Design

作者： Raj Kumar Choudhary Janeel Patel Virendra Singh Computer Architecture and Dependable Systems Laboratory Indian Institute of Technology Bombay India

Single event upsets have made modern integrated circuits more susceptible to soft errors, making their operation less reliable. In order to detect induced computational faults, we propose a fault-tolerant, low-overhead microarchitecture that detects soft errors using temporal redundancy. The idea of introducing an Early Execution Unit (EXU) at the processor frontend has been explored by previous proposals in order to execute dynamic instructions with short dependency chains expeditiously for performance improvement. However, we observe that the functional units in the EXU are idle for a significant portion of the program execution duration. Our proposed microarchitecture utilises these inactive frontend functional units in order to re-execute dynamic instructions to ascertain computational correctness. A low-overhead backend verifier leverages idle resources for redundant execution using the proposed priority-based scheduling algorithm that interleaves program execution with re-execution for error detection. Our proposal provides exhaustive transient fault coverage while improving performance by 7.5% over an existing restricted OoO microarchitecture, Freeflow Core, delivering IPC close to that of an out-of-order baseline, while being $1.78 \times $ more energy-efficient than the involuted, power-hungry out-of-order design.

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Serverless or Serverful? A Pattern-Based Approach for Exploring Hosting Alternatives 16th

Serverless or Serverful? A Pattern-Based Approach for Exp...

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16th Symposium and Summer School on Service-Oriented Computing, SummerSOC 2022

作者： Yussupov, Vladimir Breitenbücher, Uwe Brogi, Antonio Harzenetter, Lukas Leymann, Frank Soldani, Jacopo Institute of Architecture of Application Systems University of Stuttgart Stuttgart Germany Department of Computer Science University of Pisa Pisa Italy

ISBN: (纸本)9783031183034

Various cloud service models with different management requirements can be used for hosting a certain application component. For instance, more consumer-managed serverful options can be preferred if a component has special requirements related to deployment stack or scaling configuration management, whereas more provider-managed serverless alternatives can be used if no customization is needed. However, finding a suitable hosting variant based on the deployment stack or scaling configuration management requirements is cumbersome without clear guidelines. In our previous work, we introduced a set of Component Hosting Patterns that represent different management trade-offs and can help finding suitable hosting options for a component to be deployed. However, selecting the most appropriate pattern and exploring which concrete deployment alternatives can be used to technically realize the selected pattern was up to developers, thus, requiring considerable expertise in provider-specific offerings. Therefore, in this work, we (i) introduce four new complementary patterns representing abstract deployment stack customization and scaling configuration management decisions, which we (ii) combine with our Component Hosting Patterns in a new pattern language. Moreover, we (iii) introduce a method that supports application developers using the introduced pattern language as well as refining selected patterns to concrete technical deployment stacks. Finally, we (iv) show how the TOSCA modeling tool Eclipse Winery can be used to support our new method. © 2022, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Economic and social effects

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LoRa-Powered Energy-Effcient Object Detection Mechanism in Edge Computing Nodes 6

LoRa-Powered Energy-Effcient Object Detection Mechanism in E...

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6th International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud), I-SMAC 2022

作者： Jindal, Anshul Jose, Jiby Mariya Benedict, Shajulin Gerndt, Michael Technical University Munich Computer Architecture and Parallel Systems Germany Indian Institute of Information Technology Kottayam Department of Computer Science and Engg. India

ISBN: (数字)9781665469418

ISBN: (纸本)9781665469418

The ongoing accomplishments in the decades-long realization of computer vision have infused new dimensions in various research areas such as smart mobility, smart healthcare, education, finance, and so forth. Research works relating to automated object detection, deep learning-assisted data pipelines, and energy-efficient end-to-end solutions have enabled newer perceptions among researchers, albeit the existence of challenges. This paper proposes an object detection system using energy-efficient Long Range (LoRA) communication media on edge nodes such as Raspberry Pi, Coral DevBoard, and Nvidia Jetson Nano. The proposed approach utilized energy-efficient methods to collaboratively offload object detection-related tasks such as capturing images, training images, and inferring objects across a compendium of computing nodes using LoRA. In addition, this research study has attempted to reveal the inference capabilities of images on three different edge nodes. The proposed work has achieved a power difference of at least 1.2 watts during the inference period of the deep learning models without challenging the prediction accuracy with respect to the base model. © 2022 IEEE.

关键词： Object detection

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Resource scheduling techniques in cloud from a view of coordination:a holistic survey

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Frontiers of Information Technology & Electronic Engineering 2023年第1期24卷 1-40页

作者： Yuzhao WANG Junqing YU Zhibin YU School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China Center of Heterogeneous Intelligent Computer Architecture and Systems Shenzhen Institute of Advanced TechnologyChinese Academy of SciencesShenzhen 518055China

Nowadays,the management of resource contention in shared cloud remains a pending *** evolution and deployment of new application paradigms(e.g.,deep learning training and microservices)and custom hardware(e.g.,graphics processing unit(GPU)and tensor processing unit(TPU))have posed new challenges in resource management system *** solutions tend to trade cluster efficiency for guaranteed application performance,e.g.,resource over-allocation,leaving a lot of resources *** this dilemma is not easy,because different components across the software stack are ***,massive efforts have been devoted to seeking effective performance isolation and highly efficient resource *** goal of this paper is to systematically cover related aspects to deliver the techniques from the coordination perspective,and to identify the corresponding trends they ***,four topics are ***,isolation mechanisms deployed at different levels(micro-architecture,system,and virtualization levels)are reviewed,including GPU multitasking ***,resource scheduling techniques within an individual machine and at the cluster level are investigated,***,GPU scheduling for deep learning applications is described in ***,adaptive resource management including the latest microservice-related research is thoroughly ***,future research directions are discussed in the light of advanced *** hope that this review paper will help researchers establish a global view of the landscape of resource management techniques in shared cloud,and see technology trends more clearly.

关键词： Coordination Co-location Heterogeneous computing Microservice Resource scheduling techniques

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Systematic Construction of Deadlock-Free Routing for NoC Using Integer Linear Programming

Systematic Construction of Deadlock-Free Routing for NoC Usi...

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IEEE International Symposium on Embedded Multicore Socs (MCSoC)

作者： Shuang Liu Martin Radetzki Chair of Embedded Systems Institute of Computer Architecture and Computer Engineering University of Stuttgart Stuttgart Germany

Network-on-Chip (NoC) presents a promising solution for on-chip communication in highly integrated System-on-Chips (SoCs). This work addresses critical challenges in NoC design, including routing construction, application mapping, and particularly the issue of deadlocks in the widely-used wormhole routing method. In this paper, an Integer Linear Programming (ILP) approach for deadlock-free routing is proposed, applicable to arbitrary network topologies. We systematically analyze deadlock-free routing construction for mesh and torus topologies under uniform random traffic and provide alternative solutions to turn models. In the context of application-specific NoCs, application mapping, and deadlock-free routing are integrated within a single ILP. Through evaluation with several benchmark applications, it is demonstrated that the ILP method consistently delivers optimal solutions and could obtain better results than various heuristic methods within an acceptable time. Fault tolerance is also explored and existing techniques are incorporated into the ILP approach. As an illustrative example, application mapping and a 1-link-fault-tolerant deadlock-free routing for the MP3 application on a mesh network is performed.

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ERrOR: Improving Performance and Fault Tolerance Using Early Execution

ERrOR: Improving Performance and Fault Tolerance Using Early...

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IEEE Symposium on On-Line Testing (IOLTS)

作者： Raj Kumar Choudhary Janeel Patel Virendra Singh Computer Architecture and Dependable Systems Laboratory Indian Institute of Technology Bombay India

Contemporary integrated circuits are becoming increasingly susceptible to soft errors due to single-event upsets, effectively decreasing the reliability of operation. In this paper, we propose the ERrOR microarchitecture, that detects soft errors in processor operation using temporal redundancy with minimal hardware overhead. Previous proposals have explored the idea of introducing an Early Execution Unit (EXU) at the processor frontend in order to expeditiously execute dynamic instructions with short dependency chains for performance improvement. However, we observe that the functional units in the EXU are idle for a significant fraction of the program execution duration. ERrOR leverages these inactive frontend functional units to re-execute dynamic instructions for the purpose of error detection. A lightweight verifier introduced at the backend makes use of idle resources for redundant execution by interleaving program execution with re-execution for error detection. ERrOR provides exhaustive transient fault coverage while improving performance by 7.5% over an existing restricted OoO microarchitecture, Freeflow Core.

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GraphTensor: Comprehensive GNN-Acceleration Framework for Efficient Parallel Processing of Massive Datasets

GraphTensor: Comprehensive GNN-Acceleration Framework for Ef...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Junhyeok Jang Miryeong Kwon Donghyun Gouk Hanyeoreum Bae Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology (KAIST)

We present GraphTensor, a comprehensive open-source framework that supports efficient parallel neural network processing on large graphs. GraphTensor offers a set of easy-to-use programming primitives that appreciate both graph and neural network execution behaviors from the beginning (graph sampling) to the end (dense data processing). Our framework runs diverse graph neural network (GNN) models in a destination-centric, feature-wise manner, which can significantly shorten training execution times in a GPU. In addition, GraphTensor rearranges multiple GNN kernels based on their system hyperparameters in a self-governing manner, thereby reducing the processing dimensionality and the latencies further. From the end-to-end execution viewpoint, GraphTensor significantly shortens the service-level GNN latency by applying pipeline parallelism for efficient graph dataset preprocessing. Our evaluation shows that GraphTensor exhibits 1.4× better training performance than emerging GNN frameworks under the execution of large-scale, real-world graph workloads. For the end-to-end services, GraphTensor reduces training latencies of an advanced version of the GNN frameworks (optimized for multi-threaded graph sampling) by 2.4×, on average.

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Designing low-diameter interconnection networks with multi-ported host-switch graphs

Designing low-diameter interconnection networks with multi-p...

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作者： Yasudo, Ryota Nakano, Koji Koibuchi, Michihiro Matsutani, Hiroki Amano, Hideharu Graduate School of Advanced Science and Engineering Hiroshima University Hiroshima Japan Information Systems Architecture Science Research Division National Institute of Informatics Tokyo Japan Department of Information and Computer Science Keio University Yokohama Japan

A host-switch graph was originally proposed as a graph that represents a network topology of a computer systems with 1-port host computers and (Formula presented.) -port switches. It has been studied from both theoretical and practical aspects in terms of the diameter, the average shortest path length, and the performance of real applications. In recent high-performance computing systems, however, a host computer is connected to multiple switches by using InfiniBand, NVSwitch, or Omni-Path, and consequently they provide high bandwidths. Since a host-switch graph cannot represent such systems, this article extends a host-switch graph so that it can represent such systems. As a result, a host-switch graph can include multi-ported hosts. Furthermore, we propose to use multi-port hosts for reducing the diameter. We show that the diameter minimization is equivalent to solving the degree diameter problem for bipartite graphs of diameter three. Our experimental results show that we can drastically reduce the diameter as well as increasing the bandwidth and improves performance of MPI applications by up to 162% as compared with networks with single-ported hosts. © 2020 John Wiley & Sons, Ltd.

关键词： Graph theory

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