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Full life-cycle cost model for practical application of solar energy system

Energy Informatics 2025年第1期8卷

作者： Sha, Ang Xiong, Zhen Zang, Xiaolin Zhao, Wei Ge, Ruibang Yao, Wanxiang Aiello, Marco Innovation Institute for Sustainable Maritime Architecture Research and Technology Qingdao University of Technology Qingdao266033 China School of Architecture and Urban Planning Qingdao University of Technology Qingdao266033 China School of Information and Control Engineering Qingdao University of Technology Qingdao266520 China School of Continuing Education Qingdao University of Technology Qingdao266033 China Service Computing Department Institute of Architecture of Application Systems University of Stuttgart Universitätsstraße 38 Stuttgart70569 Germany

In pursuit of carbon neutrality, a swift transformation is underway in the global energy structure, marked by a consistent rise in the installed capacity of solar energy systems. Meanwhile, the substantial reduction of government subsidies in the solar industry intensifies focus on the economic viability of solar energy installations. In this study, we propose a full life-cycle cost model, named the F-LCC model, for calculating the cost of the solar energy system on the long term, e.g., 20–30 years. This model integrates replacement costs, residual value calculation, interest rate, and inflation impacts while supporting market price estimation for individual components, thereby aiding feasibility analysis in the early project phase. We design an investment cost recovery algorithm based on the F-LCC model to calculate the break-even electricity price for solar energy system. Moreover, we analyze component cost distributions, Net Present Value (NPV), and Discounted Payback Period (DPP) for grid-connected and off-grid solar energy systems with capacities of 10 kWp and 100 kWp in the Chinese market. The results show that the proposed model, compared to other models, captures the fact that payback times are longer. In a solar energy system without storage, solar panels have the highest component cost share at 28.8%. With battery storage, batteries dominate the total cost, reaching up to 74.6%. And the the grid-connected systems DPP ranging from a minimum of 5.5 to a maximum of 7.0 years by grid-connected electricity price, while off-grid systems require at least 19.9 years. The 10 kWp off-grid fixed mounting system’s break-even price being 137.1% higher than its grid-connected counterpart. In addition, tracking-mount systems offer greater cost-reduction potential than fixed installations, with the payback period reduced by 20% for 100 kWp grid-connected systems and 15% for off-grid systems. Finally, we develop a plugin based on the F-LCC model. These findings deepen unde

关键词： Commerce

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Godson-T:An Efficient Many-Core architecture for Parallel Program Executions

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Journal of Computer Science & Technology 2009年第6期24卷 1061-1073页

作者：范东睿袁楠张军超周永彬林伟宋风龙叶笑春黄河余磊龙国平张浩刘磊 Key Laboratory of Computer Systems and Architecture Institute of Computing Technology Chinese Academy of Sciences

Moore＇s law will grant computer architects ever more transistors for the foreseeable future, and the challenge is how to use them to deliver efficient performance and flexible programmability. We propose a many-core architecture, Godson- T, to attack this challenge. On the one hand, Godson-T features a region-based cache coherence protocol, asynchronous data transfer agents and hardware-supported synchronization mechanisms, to provide full potential for the high efficiency of the on-chip resource utilization. On the other hand, Godson-T features a highly efficient runtime system, a Pthreadslike programming model, and versatile parallel libraries, which make this many-core design flexibly programmable. This hardware/software cooperating design methodology bridges the high-end computing with mass programmers. Experimental evaluations are conducted on a cycle-accurate simulator of Godson-T. The results show that the proposed architecture has good scalability, fast synchronization, high computational efficiency, and flexible programmability.

关键词： many-core parallel computing multithread data communication thread synchronization runtime system

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Continual Reinforcement Learning for Digital Twin Synchronization Optimization

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IEEE Transactions on Mobile computing 2025年

作者： Tong, Haonan Chen, Mingzhe Zhao, Jun Hu, Ye Yang, Zhaohui Liu, Yuchen Yin, Changchuan Beijing University of Posts and Telecommunications Beijing Key Laboratory of Network System Architecture and Convergence Beijing Advanced Information Network Laboratory Beijing China College of Computing and Data Science Singapore University of Miami Department of Electrical and Computer Engineering Frost Institute for Data Science and Computing Coral Gables33146 United States University of Miami Department of Industrial and Systems Engineering Coral Gables33146 United States Zhejiang University College of Information Science and Electronic Engineering Hangzhou310027 China North Carolina State University Department of Computer Science RaleighNC27695 United States Beijing Key Laboratory of Network System Architecture and Convergence China Beijing University of Posts and Telecommunications Beijing Advanced Information Network Laboratory Beijing100876 China

This article investigates the adaptive resource allocation scheme for digital twin (DT) synchronization optimization over dynamic wireless networks. In our considered model, a base station (BS) continuously collects factory physical object state data from wireless devices to build a real-time virtual DT system for factory event analysis. Due to continuous data transmission, maintaining DT synchronization must use extensive wireless resources. To address this issue, a subset of devices is selected to transmit their sensing data, and resource block (RB) allocation is optimized. This problem is formulated as a constrained Markov process (CMDP) problem that minimizes the long-term mismatch between the physical and virtual systems. To solve this CMDP, we first transform the problem into a dual problem that refines RB constraint impacts on device scheduling strategies. We then propose a continual reinforcement learning (CRL) algorithm to solve the dual problem. The CRL algorithm learns a stable policy across historical experiences for quick adaptation to dynamics in physical states and network capacity. Simulation results show that the CRL can adapt quickly to network capacity changes and reduce normalized root mean square error (NRMSE) between physical and virtual states by up to 55.2%, using the same RB number as traditional methods. © 2025 IEEE. All rights reserved.

关键词： Markov processes

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Context-Aware Human Behavior Prediction Using Multimodal Large Language Models: Challenges and Insights

arXiv

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arXiv 2025年

作者： Liu, Yuchen Lerch, Lino Palmieri, Luigi Rudenko, Andrey Koch, Sebastian Ropinski, Timo Aiello, Marco Corporate Sector Research and Advance Engineering Robert Bosch GmbH Germany Service Computing Department Institute of Architecture of Application Systems University of Stuttgart Germany Visual Computing Group Ulm University Germany

Predicting human behavior in shared environments is crucial for safe and efficient human-robot interaction. Traditional data-driven methods to that end are pre-trained on domain-specific datasets, activity types, and prediction horizons. In contrast, the recent breakthroughs in Large Language Models (LLMs) promise open-ended cross-domain generalization to describe various human activities and make predictions in any context. In particular, Multimodal LLMs (MLLMs) are able to integrate information from various sources, achieving more contextual awareness and improved scene understanding. The difficulty in applying general-purpose MLLMs directly for prediction stems from their limited capacity for processing large input sequences, sensitivity to prompt design, and expensive fine-tuning. In this paper, we present a systematic analysis of applying pre-trained MLLMs for context-aware human behavior prediction. To this end, we introduce a modular multimodal human activity prediction framework that allows us to benchmark various MLLMs, input variations, In-Context Learning (ICL), and autoregressive techniques. Our evaluation indicates that the best-performing framework configuration is able to reach 92.8% semantic similarity and 66.1% exact label accuracy in predicting human behaviors in the target frame. © 2025, CC BY.

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Autotuning wavefront applications for multicore multi-GPU hybrid architectures

Autotuning wavefront applications for multicore multi-GPU hy...

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2014 International Workshop on Programming Models and Applications for Multicores and Manycores, PMAM 2014

作者： Mohanty, Siddharth Cole, Murray Institute for Computing Systems Architecture University of Edinburgh United Kingdom

ISBN: (纸本)9781450326551

Manual tuning of applications for heterogeneous parallel systems is tedious and complex. Optimizations are often not portable, and the whole process must be repeated when moving to a new system, or sometimes even to a diffierent problem size. Pattern-based programming models provide structure which can assist in the creation of autotuners for such problems. We present a machine learning based auto-tuning framework which partitions the work created by applications which follow the wavefront pattern across systems comprising multicore CPUs and multiple GPU accelerators. The use of a pattern facilitates training on synthetically generated instances. Exhaustive search space exploration on real applications indicates that correct setting of the tuning factors leads to a maximum of 20x speedup over an optimized sequential baseline, with an average of 7.8x. Our machine learned heuristics obtain 98% of this speed-up, averaged across range of applications and architectures. Categories and Subject Descriptors C.4 [Performance of systems]: Design Studies;D.1.3 [Programming Techniques]: Concurrent Programming- Parallel programming.

关键词： Graphics processing unit

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Reactive grid scheduling of DAG applications

Reactive grid scheduling of DAG applications

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IASTED International Conference on Parallel and Distributed computing and Networks, PDCN 2007

作者： Hernandez, Israel Cole, Murray Institute for Computing Systems Architecture School of Informatics University of Edinburgh

ISBN: (纸本)9780889866379

We consider the problem of scheduling parallel applications, represented by directed acyclic graphs (DAGs), onto Grid style resource pools. The core issues are that the availability and performance of grid resources, which are already by their nature heterogeneous, can be expected to vary dynamically, even during the course of an execution. Typical scheduling methods in the literature partially address this issue because they consider static heterogenous computing environments (i.e. heterogeneous resources are dedicated and unchanging over time). This paper presents the Grid Task Positioning GTP scheduling method, which addresses the problem by allowing rescheduling of an executing application in response to significant variations in resource characteristics. GTP considers the impact of partial completion of tasks and task migration. We compare the performance of GTP with that of the well-known, and static, Heterogeneous Earliest Finish Time (HEFT) algorithm.

关键词： Grid computing

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SuperCoP: A general, correct, and performance-efficient supervised memory system 12

SuperCoP: A general, correct, and performance-efficient supe...

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ACM computing Frontiers Conference, CF '12

作者： Rajaram, Bharghava Nagarajan, Vijay McPherson, Andrew J. Cintra, Marcelo Institute for Computing Systems Architecture University of Edinburgh Edinburgh United Kingdom

ISBN: (纸本)9781450312158

Supervised memory systems maintain additional metadata for each memory address accessed by the program, to control and monitor accesses to the program data. Supervised systems find use in several applications including memory checking, synchronization, race detection, and transactional memory. Conventional memory instructions are replaced by supervised memory instructions (SMIs) which operate on both data and metadata atomically. Existing proposals for supervised memory systems assume sequential consistency. Recently, Bobba et al. [4] demonstrated the correctness issues (imprecise exceptions and metadata read reordering) in naively applying supervision to Total-Store-Order, and proposed two solutions - TSOall and TSOdata - for overcoming the correctness issues. TSOall solves correctness issues by forcing SMIs to perform in order, but performs similar to SC, since supervised writes cannot retire into the write-buffer. TSOdata, while allowing supervised writes to retire into the write-buffer, works correctly for only a subset of supervision schemes. In this paper we observe that correctness is ensured as long as SMIs read and process their metadata in order. We propose SuperCoP, a supervised memory system for relaxed memory models in which SMIs read and process metadata before retirement, while allowing data and metadata writes to retire into the write-buffer. Since SuperCoP separates metadata reads and their processing from the writes, we propose a simple mechanism - in the form of cache block level locking at the directory - to ensure atomicity. Our experimental results show that SuperCoP performs better than TSOall by 16.8%. SuperCoP also performs better than TSOdata by 6%, even though TSOdata is not general. © 2012 ACM.

关键词： Metadata

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A parallel dynamic binary translator for efficient multi-core simulation

A parallel dynamic binary translator for efficient multi-cor...

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作者： Almer, Oscar Böhm, Igor Von Koch, Tobias Edler Franke, Björn Kyle, Stephen Seeker, Volker Thompson, Christopher Topham, Nigel Institute for Computing Systems Architecture University of Edinburgh Edinburgh United Kingdom

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc MultiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core x86 host machine for as many as 2,048 target processors whilst exhibiting minimal and near constant overhead, including memory considerations. © 2012 Springer Science+Business Media New York.

关键词： Embedded systems

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Fast source-level data assignment to dual memory banks 08

Fast source-level data assignment to dual memory banks

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11th International Workshop on Software and Compilers for Embedded systems, SCOPES 2008

作者： Murray, Alastair Franke, Björn University of Edinburgh School of Informatics Institute for Computing Systems Architecture United Kingdom

ISBN: (纸本)9781450378437

Due to their streaming nature memory bandwidth is critical for most digital signal processing applications. To accommodate for these bandwidth requirements digital signal processors are typically equipped with dual memory banks that enable simultaneous access to two operands if the data is partitioned appropriately. Fully automated and compiler integrated approaches to data partitioning and memory bank assignment, however, have found little acceptance by DSP software developers. This is partly due to their inflexibility and inability to cope with certain manual data pre-assignments, e.g. due to I/O constraints. In this paper we present a different and more flexible approach, namely source-level dual memory assignment where code generation targets DSP-C, a standardised C language extension widely supported by industrial C compilers for DSPs. Additionally, we present a novel partitioning algorithm based on soft colouring that is more efficient and scalable than the currently known best integer linear programming algorithm, whilst achieving competitive code quality. We have evaluated our scheme on an Analog Devices TigerSHARC DSP and achieved speedups of up to 1.57 on 13 UTDSP benchmarks. © 2008 by EDAA.

关键词： Digital signal processing

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Computer architecture Simulation models

Computer architecture Simulation models

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ITiCSE06: 11th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education

作者： Ibbett, Roland N. Diaz y Carballo, J.C. Dolman, D.A.W. Institute for Computing Systems Architecture School of Informatics University of Edinburgh United Kingdom

ISBN: (纸本)1595930558

Simulation models of a variety of computer architectures have been created using HASE, a Hierarchical Computer architecture design and Simulation Environment. Some of these models were previously available as applets but using the models directly in a new version of HASE, itself now available for downloading, has proved more satisfactory.

关键词： Computer architecture

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