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Array Recovery and High-Level Transformations for DSP Applications

ACM Transactions on Embedded computing systems 2003年第2期2卷 132-162页

作者： Franke, Björn Institute for Computing Systems Architecture (ICSA) Division of Informatics University of Edinburgh JCMB King‗s Buildings Mayfield Rd. EH9 3JZ United Kingdom

Efficient implementation of DSP applications is critical for many embedded systems. Optimizing compilers for application programs, written in C, largely focus on code generation and scheduling, which, with their growing maturity, are providing diminishing returns. As DSP applications typically make extensive use of pointer arithmetic, the alternative use of high-level, source-to-source, transformations has been largely ignored. This article develops an array recovery technique that automatically converts pointers to arrays, enabling the empirical evaluation of high-level transformations. High-level techniques were applied to the DSPstone benchmarks on three platforms: TriMedia TM-1000, Texas Instruments TMS320C6201, and the Analog Devices SHARC ADSP- 21160. On average, the best transformation gave a factor of 2.43 improvement across the platforms. In certain cases, a speedup of 5.48 was found for the SHARC, 7.38 for the TM-1, and 2.3 for the C6201. These preliminary results justify pointer to array conversion and further investigation into the use of high-level techniques for embedded compilers. Copyright © 2003, ACM. All rights reserved.

关键词： Algorithms dataflow graphs embedded processors Experimentation high-level transformations Measurement Pointer conversion

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Autotuning Wavefront Abstractions for Heterogeneous architectures

Autotuning Wavefront Abstractions for Heterogeneous Architec...

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Workshop on architecture and Multi-Core Applications (WAMCA)

作者： Siddharth Mohanty Murray Cole Institute for Computing Systems Architecture University of Edinburgh Edinburgh UK

We present our auto tuned heterogeneous parallel programming abstraction for the wave front pattern. An exhaustive search of the tuning space indicates that correct setting of tuning factors can average 37x speedup over a sequential baseline. Our best automated machine learning based heuristic obtains 92% of this ideal speedup, averaged across our full range of wave front examples.

关键词： Tiles Graphics processing units Tuners Support vector machines Kernel Parallel processing

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Computer architecture simulation applets for use in teaching

Computer architecture simulation applets for use in teaching

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Frontiers in Education (FIE) Conference

作者： R. Ibbett F. Mallet Institute for Computing Systems Architecture University of Edinburgh Edinburgh UK

Visualisation of the activities which occur inside a computer is an important aspect of computer architecture education. At the University of Edinburgh we are using a hierarchical computer architecture design and simulation environment (HASE) to build a number of architectural models for use in research and teaching. A new facility within HASE, JavaHASE, allows models to be translated into applets which can be accessed via the WWW. JavaHASE applets are programmable simulation models in which the code and data memory contents can be altered, the simulation re-run in the applet and the results used to visualise the activities taking place within the model (data movements, state changes, register/memory content changes, etc). These applets are being used in various ways in teaching.

关键词： Computer architecture Computational modeling Computer simulation Java World Wide Web Discrete event simulation Animation Computer science education Data visualization Arithmetic

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High Speed Cycle Approximate Simulation for Cache-Incoherent MPSoCs

High Speed Cycle Approximate Simulation for Cache-Incoherent...

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International Conference on Embedded Computer systems: architectures, Modeling and Simulation

作者： Christopher Thompson Miles Gould Nigel Topham Institute for Computing Systems Architecture University of Edinburgh United Kingdom

ISBN: (纸本)9781479901043

We present a new high speed cycle-approximate simulator, addressing an important, neglected category of multi-core systems: deeply-embedded cache-incoherent MPSoCs. We take advantage of the unique properties of these systems to increase the parallelism of the simulation. In doing so we achieve performance not possible using previous simulation techniques, without compromising the accuracy of the results. We present quantitative performance results across a large range of simulated NoC designs, comprising 1 to 64 cores. On average we simulate at 5.9 MIPS, with simulation speeds reaching 373 MIPS in the best case. Comparing against FPGA implementations we demonstrate that the simulator manages this with an average timing error of only 2.1%.

关键词： MIPS FPGA MPSoCs

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Understanding travel behavior adjustment under COVID-19

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Communications in Transportation Research 2022年第1期2卷 152-166页

作者： Wenbin Yao Jinqiang Yu Ying Yang Nuo Chen Sheng Jin Youwei Hu Congcong Bai Institute of Intelligent Transportation Systems Zhejiang UniversityHangzhouChina Center for Balance Architecture Zhejiang UniversityHangzhouChina Alibaba Cloud Computing Co.Ltd. HangzhouChina School of Behavioural and Health Sciences Australian Catholic UniversitySydneyAustralia Pengcheng Laboratory ShenzhenChina

The outbreak and spreading of the COVID-19 pandemic have had a significant impact on transportation *** analyzing the impact of the pandemic on the transportation system,the impact of the pandemic on the social economy can be reflected to a certain extent,and the effect of anti-pandemic policy implementation can also be *** addition,the analysis results are expected to provide support for policy ***,most of the relevant studies analyze the impact of the pandemic on the overall transportation system from the macro perspective,while few studies quantitatively analyze the impact of the pandemic on individual spatiotemporal travel *** on the license plate recognition(LPR)data,this paper analyzes the spatiotemporal travel patterns of travelers in each stage of the pandemic progress,quantifies the change of travelers'spatiotemporal behaviors,and analyzes the adjustment of travelers'behaviors under the influence of the *** are three different behavior adjustment strategies under the influence of the pandemic,and the behavior adjustment is related to the individual's past travel *** paper quantitatively assesses the impact of the COVID-19 pandemic on individual travel *** the method proposed in this paper can be used to quantitatively assess the impact of any long-term emergency on individual micro travel behavior.

关键词： COVID-19 Travel pattern Travel behavior adjustment Prefix-span algorithm Random forest

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Generating different realistic humanoid motion

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16th International Conference on Artificial Reality and Telexistence, ICAT 2006

作者： Li, Zhenbo Deng, Yu Li, Hua Key Lab. of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University of Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)3540497765

Different realistic humanoid motion can be used in vary situations in animation. It also plays an important role in virtual reality. In this paper, we propose a novel method to generate different realistic humanoid motion automatically. Firstly, eigenvectors of a motion sequence is computed using principle component analysis. The principle components are served as "virtual joints" in our system. The number of "virtual joints" can be used to control the realistic level of motions. After given the "virtual joints" number, the actual joints' parameters of new motion are computed using the selected "virtual joints". The experiments illuminate that this method has good ability to generate different realistic level motions. © 2006 Springer-Verlag Berlin/Heidelberg.

关键词： Principal component analysis

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Resource Sharing in Custom Instruction Set Extensions

Resource Sharing in Custom Instruction Set Extensions

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Symposium on Application Specific Processors, SASP

作者： Marcela Zuluaga Nigel Topham Institute for Computing Systems ArchitectureSchool of Informatics University of Edinburgh UK Institute for Computing Systems Architecture School of Informatics University of Edinburgh UK

Customised processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must take into account; die area and energy efficiency are equally important. Resource sharing during synthesis of instruction set extensions (ISEs) can reduce significantly the die area and energy consumption of a customised processor. This may increase the number of custom instructions that can be synthesized with a given area budget. Resource sharing involves combining the graph representations of two or more ISEs which contain a similar sub-graph. This coupling of multiple sub-graphs, if performed naively, can increase the latency of the extension instructions considerably. And yet, as we show in this paper, an appropriate level of resource sharing provides a significantly simpler design with only modest increases in average latency for extension instructions. Based on existing resource-sharing techniques, this study presents a new heuristic that controls the degree of resource sharing between a given set of custom instructions. Our main contributions are the introduction of a parametric method for exploring the trade-offs that can be achieved between instruction latency and implementation complexity, and the coupling of design-space exploration with fast area-delay models for the operators comprising each ISE. We present experimental evidence that our heuristic exposes a broad range of design points, allowing advantageous trade-offs between die area and latency to be found and exploited.

关键词： Resource management Costs Delay Application specific integrated circuits Computer aided instruction Computer architecture Informatics Energy efficiency Application specific processors Field programmable gate arrays

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An adaptive parallel pipeline pattern for grids

An adaptive parallel pipeline pattern for grids

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Horacio Gonzalez-Velez Murray Cole Institute for Computing Systems Architecture School of Informatics University of Edinburgh UK

This paper introduces an adaptive parallel pipeline pattern which follows the GRASP (grid-adaptive structured parallelism) methodology. GRASP is a generic methodology to incorporate structural information at compile time into a parallel program that enables it to adapt automatically to dynamic variations in resource performance. GRASP instruments the pipeline with a series of pragmatic rules, which depend on particular performance thresholds based on the computation/communication patterns of the program and the availability of resources in the grid. Our parallel pipeline pattern is implemented as a parameterisable C/MPI API using a variable-size input data vector and a stage function array. We have evaluated its efficiency using a numerical benchmark stage function in a non-dedicated computational grid environment.

关键词： Pipelines Grid computing Concurrent computing Parallel processing Throughput Delay Computer architecture Informatics Electronic mail Instruments

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Empirical evaluation of data transformations for network infrastructure applications

Empirical evaluation of data transformations for network inf...

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International Conference on Embedded Computer systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Damon Fenacci Björn Franke Institute of Computing Systems Architecture School of Information University of Edinburgh UK

It is estimated that the amount of data coming out of an optical fibre is doubling every nine months and, thus, the growth rate in network bandwidth by far exceeds that of transistor density stated by Moore's law. This causes excessive strain on network infrastructure nodes such as routers which need to operate at line rate in order to keep up with the external bandwidth requirements. Consequently, manufacturers of network processors have developed a wide range of technologies including highly parallel and specialised architectures to cope with ever increasing processing demands. Software tool support, however, lags behind and most research in compiling for network processors has focused on improved sequential and parallel code generation. In this paper we show that not code, but data organisation is the key obstacle to overcome in order to achieve high performance on network infrastructure applications. We evaluate three specialised data transformations (structure splitting, array regrouping, and software caching) against the industrial EEMBC networking benchmarks and real-world data sets. We demonstrate that speedups of up to 2.62 can be achieved, but at the same time no single solution performs equally well across all network traffic scenarios. This clearly indicates that adaptive data transformation schemes are necessary to ensure optimal performance under varying network loads.

关键词： IP networks Benchmark testing Payloads Data structures Internet Reduced instruction set computing

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HTN planning domain for deployment of cloud applications

arXiv

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arXiv 2021年

作者： Georgievski, Ilche Service Computing Department Institute for Architecture of Application Systems University of Stuttgart

Cloud providers are facing a complex problem in configuring software applications ready for deployment on their infrastructures. Hierarchical Task Network (HTN) planning can provide effective means to solve such deployment problems. We present an HTN planning domain that models deployment problems as found in realistic Cloud environments. Copyright © 2021, The Authors. All rights reserved.

关键词： Application programs

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