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Symposium on Application Specific Processors, SASP

作者： Marcela Zuluaga Theo Kluter Philip Brisk Nigel Topham Paolo Ienne School of Informatics Institute for Computing Systems Architecture University of Edinburgh Edinburgh UK School of Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

Multicycle instruction set extensions (ISE) can be pipelined in order to increase their throughput; however, typical program traces seldom contain consecutive calls to the same ISE that would allow this temporal parallelism. Often, there are intermittent calls to branch instructions, at a minimum, that prevent the pipelined execution of subsequent calls to the same ISE within a loop. What is needed is ISEs that cover an entire loop body, which can create a stream of repeated calls to the same ISE during program execution; this, in turn, permits the use of hardware pipelining. To address this concern, we introduce a new type of ISE that borrows ideas from zero overhead loop instructions to permit pipelined execution of loops. To further expose instruction level parallelism, the ISE supports loops whose bodies form hyperblocks, which are regions of program control flow that have multiple exits (including loop iterations and break points within loops). These ISEs broaden the scope of instruction level parallelism and obtain higher speed ups compared to traditional ISEs, primarily through pipelining, the exploitation of spatial parallelism, and reducing the overhead of control flow statements and branches.

关键词： Pipeline processing Parallel processing Coprocessors Hardware Computer aided instruction Concurrent computing Electronic mail Costs Design automation Application specific processors

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Fast source-level data assignment to dual memory banks 08

Fast source-level data assignment to dual memory banks

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11th International Workshop on Software and Compilers for Embedded systems, SCOPES 2008

作者： Murray, Alastair Franke, Björn University of Edinburgh School of Informatics Institute for Computing Systems Architecture United Kingdom

ISBN: (纸本)9781450378437

Due to their streaming nature memory bandwidth is critical for most digital signal processing applications. To accommodate for these bandwidth requirements digital signal processors are typically equipped with dual memory banks that enable simultaneous access to two operands if the data is partitioned appropriately. Fully automated and compiler integrated approaches to data partitioning and memory bank assignment, however, have found little acceptance by DSP software developers. This is partly due to their inflexibility and inability to cope with certain manual data pre-assignments, e.g. due to I/O constraints. In this paper we present a different and more flexible approach, namely source-level dual memory assignment where code generation targets DSP-C, a standardised C language extension widely supported by industrial C compilers for DSPs. Additionally, we present a novel partitioning algorithm based on soft colouring that is more efficient and scalable than the currently known best integer linear programming algorithm, whilst achieving competitive code quality. We have evaluated our scheme on an Analog Devices TigerSHARC DSP and achieved speedups of up to 1.57 on 13 UTDSP benchmarks. © 2008 by EDAA.

关键词： Digital signal processing

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Fast cycle-approximate instruction set simulation 08

Fast cycle-approximate instruction set simulation

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11th International Workshop on Software and Compilers for Embedded systems, SCOPES 2008

作者： Franke, Björn Institute for Computing Systems Architecture School of Informatics University of Edinburgh Mayfield Road Edinburgh EH9 3JZ United Kingdom

ISBN: (纸本)9781450378437

Instruction set simulators are indispensable tools in both ASIP design space exploration and the software development and optimisation process for existing platforms. Despite the recent progress in improving the speed of functional instruction set simulators cycle-accurate simulation is still prohibitively slow for all but the most simple programs. This severely limits the applicability of cycle-accurate simulators in the performance evaluation of complex embedded applications. In this paper we present a novel approach, namely the prediction of cycle counts based on information gathered during fast functional simulation and prior training. We have evaluated our approach against a cycle-accurate ARM v5 architecture simulator and a large set of benchmarks. We demonstrate it is capability of providing highly accurate performance predictions with an average error of less than 5.8% at a fraction of the time for cycle-accurate simulation. © 2008 by EDAA.

关键词： Simulators

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Resource Sharing in Custom Instruction Set Extensions

Resource Sharing in Custom Instruction Set Extensions

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Symposium on Application Specific Processors, SASP

作者： Marcela Zuluaga Nigel Topham Institute for Computing Systems ArchitectureSchool of Informatics University of Edinburgh UK Institute for Computing Systems Architecture School of Informatics University of Edinburgh UK

Customised processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must take into account; die area and energy efficiency are equally important. Resource sharing during synthesis of instruction set extensions (ISEs) can reduce significantly the die area and energy consumption of a customised processor. This may increase the number of custom instructions that can be synthesized with a given area budget. Resource sharing involves combining the graph representations of two or more ISEs which contain a similar sub-graph. This coupling of multiple sub-graphs, if performed naively, can increase the latency of the extension instructions considerably. And yet, as we show in this paper, an appropriate level of resource sharing provides a significantly simpler design with only modest increases in average latency for extension instructions. Based on existing resource-sharing techniques, this study presents a new heuristic that controls the degree of resource sharing between a given set of custom instructions. Our main contributions are the introduction of a parametric method for exploring the trade-offs that can be achieved between instruction latency and implementation complexity, and the coupling of design-space exploration with fast area-delay models for the operators comprising each ISE. We present experimental evidence that our heuristic exposes a broad range of design points, allowing advantageous trade-offs between die area and latency to be found and exploited.

关键词： Resource management Costs Delay Application specific integrated circuits Computer aided instruction Computer architecture informatics Energy efficiency Application specific processors Field programmable gate arrays

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An adaptive parallel pipeline pattern for grids

An adaptive parallel pipeline pattern for grids

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Horacio Gonzalez-Velez Murray Cole Institute for Computing Systems Architecture School of Informatics University of Edinburgh UK

This paper introduces an adaptive parallel pipeline pattern which follows the GRASP (grid-adaptive structured parallelism) methodology. GRASP is a generic methodology to incorporate structural information at compile time into a parallel program that enables it to adapt automatically to dynamic variations in resource performance. GRASP instruments the pipeline with a series of pragmatic rules, which depend on particular performance thresholds based on the computation/communication patterns of the program and the availability of resources in the grid. Our parallel pipeline pattern is implemented as a parameterisable C/MPI API using a variable-size input data vector and a stage function array. We have evaluated its efficiency using a numerical benchmark stage function in a non-dedicated computational grid environment.

关键词： Pipelines Grid computing Concurrent computing Parallel processing Throughput Delay Computer architecture informatics Electronic mail Instruments

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Formally specifying and verifying mobile agents - Model checking mobility: The MobiOZ approach

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International Journal of Agent-Oriented Software Engineering 2008年第4期2卷 449-474页

作者： Taguchi, Kenji Dong, Jin Song Information Systems Architecture Research Division Grace Center National Institute of Informatics 2-1-2 Hitotsubashi Chiyoda-ku Tokyo 101 8430 Japan Computer Science Department School of Computing National University of Singapore 3 Science Drive 2 Singapore 117543 Singapore

The notion of the mobile agent has been around for over a decade in order to capture the new form of computation in communication networks. A mobile agent is a computing entity which can move around different hosts on the network, carrying its state and procedures. Mobile Object-Z (MobiOZ), which is designed to provide a practical means to the specifiers who are working on mobile agent applications, is an extended notation of Object-Z, with mobile and communication primitives for specifying and verifying mobile agent applications. In this paper, we will give an overview of the MobiOZ notation and present its semantic foundation, then demonstrate how the specifications in MobiOZ can be simulated and verified by SPIN, a model checker, by translating MobiOZ specifications into PROcess MEta LAnguage (PROMELA), a process-based formal specification language of SPIN. © 2008, Inderscience Publishers.

关键词： Formal specification

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On the scalability of storage sub-system back-end networks

On the scalability of storage sub-system back-end networks

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International Symposium on Performance Evaluation of Computer & Telecommunication systems SPECTS

作者： Yan Li Tim Courtney Roland N. Ibbett Nigel Topham Institute for Computing Systems Architecture School of Informatics University of Edinburgh UK Xyratex Havant Hampshire UK

ISBN: (纸本)9781424434497

As the number of disks in a storage sub-system keeps increasing, the back-end network may become the bottleneck and thus impose a constraint on system performance. Unfortunately, there is no visible literature base on storage back-end network bottlenecks and scalability. This paper studies the scalability of the back-end network by answering two questions: (1) which factors affect the back-end network bandwidth requirements of disks? (2) given an interconnection network, how many disks can be connected to the system? Both analytical and simulation approaches are used. The major results are: (1) the back-end network bandwidth requirement per disk is primarily determined by workload features and the stripe unit size; (2) the number of disks that a system can accommodate is limited by the back-end network bandwidth. systems with smaller stripe unit size have better network scalability. We present accurate quantitative results on the bandwidth requirement and the back-end network saturation points for a number of conventional system configurations under OLTP-like workloads and sequential workloads. We believe that these results provide practical guidance for storage sub-system design.

关键词： Scalability Bandwidth Costs Analytical models Multiprocessor interconnection networks System performance Computer networks Computer architecture informatics Optical fiber devices

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Reactive grid scheduling of DAG applications

Reactive grid scheduling of DAG applications

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IASTED International Conference on Parallel and Distributed computing and Networks, PDCN 2007

作者： Hernandez, Israel Cole, Murray Institute for Computing Systems Architecture School of Informatics University of Edinburgh

ISBN: (纸本)9780889866379

We consider the problem of scheduling parallel applications, represented by directed acyclic graphs (DAGs), onto Grid style resource pools. The core issues are that the availability and performance of grid resources, which are already by their nature heterogeneous, can be expected to vary dynamically, even during the course of an execution. Typical scheduling methods in the literature partially address this issue because they consider static heterogenous computing environments (i.e. heterogeneous resources are dedicated and unchanging over time). This paper presents the Grid Task Positioning GTP scheduling method, which addresses the problem by allowing rescheduling of an executing application in response to significant variations in resource characteristics. GTP considers the impact of partial completion of tasks and task migration. We compare the performance of GTP with that of the well-known, and static, Heterogeneous Earliest Finish Time (HEFT) algorithm.

关键词： Grid computing

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Reports of the AAAI 2008 Spring Symposia

Reports of the AAAI 2008 Spring Symposia

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作者： Balduccini, Marcello Baral, Chitta Brodaric, Boyan Colton, Simon Fox, Peter Gutelius, David Hinkelman, Knut Horswill, Ian Huberman, Bernardo Hudlicka, Eva Lerman, Kristina Lisetti, Christine McGuinness, Deborah Maher, Mary Lou Musen, Mark A. Sahami, Mehran Sleeman, Derek Thönssen, Barbara Velasquez, Juan Ventura, Dan Eastman Kodak Company Arizona State University Tempe AZ United States Geological Survey of Canada Department of Computing Imperial College London United Kingdom National Center for Atmospheric Research Artificial Intelligence Center SRI International Menlo Park CA United States University of Applied Sciences Zurich Switzerland Department of Computer Science Northwestern University Evanston IL United States Social Computing Lab. Hewlett-Packard Laboratories Psychometric Associates USC Information Sciences Institute University of Southern California Los Angeles CA United States Computer Science Department University of Southern California Los Angeles CA United States School of Computing and Information Sciences Florida International University Miami FL United States Rensselaer Polytechnic Institute Information and Intelligent Systems Division National Science Foundation University of Sydney Sydney NSW Australia Faculty of Architecture Design and Planning University of Sydney Sydney NSW Australia Department of Medicine Biomedica Informatics Research Department Stanford University Stanford CA United States Computer Science Department Stanford University Stanford CA United States Department of Computing Science University of Aberdeen Aberdeen United Kingdom MIT CSAIL Department of Computer Science Brigham Young University Provo UT United States

The Association for the Advancement of Artificial Intelligence (AAAI) was pleased to present the AAAI 2008 Spring Symposium Series, held Wednesday through Friday, March 26-28, 2008, at Stanford University, California. The eight symposia were titled (1) AI Meets Business Rules and Process Management, (2) architectures for Intelligent Theory-Based Agents, (3) Creative Intelligent systems, (4) Emotion, Personality, and Social Behavior, (5) Semantic Scientific Knowledge Integration, (6) Social Information Processing, (7) Symbiotic Relationships between Semantic Web and Knowledge Engineering, (8) Using Al to Motivate Greater Participation in Computer Science. The goal of the AI Meets Business Rules and Process Management AAAI symposium was to investigate the various approaches and standards to represent business rules, business process management, and the semantic web with respect to expressiveness and reasoning capabilities. The focus of the architectures ror Intelligent Theory-Based Agents AAAI symposium was the definition or architectures for intelligent theory-based agents, comprising languages, knowledge representation methodologies, reasoning algorithms, and control loops. The Creative Intelligent systems symposium included five major discussion sessions and a general poster session (in which all contributing papers were presented). The purpose of this symposium was to explore the synergies between creative cognition and intelligent systems. The goal of the Emotion, Personality, and Social Behavior symposium was to examine fundamental issues in affect and personality in both biological and artificial agents, focusing on the roles of these factors in mediating social behavior. The Semantic Scientific Knowledge Integration symposium brought together the semantic technologies community with the scientific information technology community in an effort to build the general semantic science information community. The Social Information Processing symposium's goal was to

关键词： Knowledge representation

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Reliable DAG scheduling on grids with rewinding and migration 1

Reliable DAG scheduling on grids with rewinding and migratio...

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1st International Conference on Networks for Grid Applications, GridNets 2007

作者： Hernandez, Israel Cole, Murray Institute for Computing Systems Architecture School of Informatics University of Edinburgh United Kingdom

ISBN: (纸本)9789639799028

Fault tolerance is an important issue in Grid computing as the availability of Grid resources can not be guaranteed. Effective scheduling methods must include fault tolerant mechanisms to preserve the execution of DAG applications, despite the presence of a processor failure. To address this, we designed the DAG rewinding mechanism, an event-driven process executed when a failure is detected at some rescheduling point. The rewinding mechanism preserves the execution of the application by recomputing and migrating those tasks which will disrupt the forward execution of succeeding tasks. The mechanism rewinds the progress of the application to a previous state, thereby preserving the execution despite the failed processor(s). This paper extends our work in the area by adding the rewinding mechanism to our previous dynamic scheduling methods GTP and GTP=c. We show how to integrate the rewinding mechanism within our dynamic execution models. Copyright 2007 ICST.

关键词： Fault tolerance

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