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Methods of accelerated characterization of VLSI cell libraries with prescribed accuracy control

Russian microelectronics 2011年第7期40卷 476-482页

作者： Gavrilov, S.V. Gudkova, O.N. Egorov, Yu.B. Institute for Design Problems in Microelectronics Russian Academy of Sciences Russia

The problems of simulation and characterization of VLSI standard cell libraries designed on the basis of semiconducting CMOS-technologies of the deep submicron and nanometer level are considered. The acceleration methods of the characterization process resulted in the identification of parameters of logic cell macromodels under the multiple simulation of cells on a circuit level for different versions of input actions and under the values of process-dependent parameters and modes of circuit operation. The algorithms of constructing the circuit characterization are directed at decreasing computational expenditures and ensuring the required accuracy of the macromodels. The results of the comparative analysis of different versions of the proposed algorithms are given. © Pleiades Publishing, Ltd., 2011.

关键词： Cells

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Antenna Array and Feed-Backward Equalizer as Single Adaptive Device

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Radioelectronics and Communications Systems 2021年第9期64卷 482-493页

作者： Djigan, Victor I. Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia

Abstract: This paper considers an adaptive antenna array (AAA) with its weight factors combined with those of Feed-Forward (FF) part of a channel equalizer, while the array output signal is combined with that of Feed-Backward (FB) part of the equalizer. Such an array and distributed equalizer operate as a single multichannel adaptive filter providing the possibility of receiving a useful signal under conditions of its multipathing and in the presence of signals of external interference sources. The paper presents the architecture of antenna array/equalizer and the mathematical description of its multichannel adaptive algorithms, such as recursive least-squares (RLS) algorithm based on the Matrix Inversion Lemma (MIL), QR-decomposition and Householder’s transformation with quadratic computational complexity, and also simple algorithms based on the least squares (LS) criterion, normalized LS (NLS) and affine projection (AP) algorithms with linear computational complexity. The simulation results of the linear antenna array with eight antennas/channels, which receives a useful 16-PSK signal having passed through a two-ray communication channel in the presence of one to four interference sources with signal-to-interference ratio (SIR) of –30 dB for each interference and the signal-to-noise ratio (SNR) of 10–30 dB in the array channels, demonstrate the efficiency of the solution proposed. © 2021, Pleiades Publishing, Ltd.

关键词： Equalizers

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The analysis of the performance of nanometer intellectual property blocks based on interval simulation

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Russian microelectronics 2013年第7期42卷 396-402页

作者： Gavrilov, S.V. Gudkova, O.N. Stempkovskiy, A.L. Institute of Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia

The problems of logic and timing analysis, arising in the design and optimization stages of complex functional VLSI units, are considered. The new method of logic and timing simulation of CMOS circuits from interval estimates, which ensure the integration of two contrary approaches to solving the problem of the performance analysis, namely, the analysis of critical paths and simulation of test sequences, is proposed. The selection of the interval approach is determined by the substantial increase in specific weights of parameter variations of nanometer elements in the timing calculations. © 2013 Pleiades Publishing, Ltd.

关键词： Timing circuits

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Analysis of oscillator synchronization conditions

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Russian microelectronics 2011年第7期40卷 520-525页

作者： Gourary, M.M. Ulyanov, S.L. Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia

The problem of determining the synchronization conditions of an arbitrary oscillator by a small periodic arbitrary waveform signal is considered. It is shown that the problem solution can be found from the existence conditions of small-signal linear system solution. An explicit equation for the oscillator locking range is derived, which can be easily included into a circuit simulation program. A comparison with well-known equations is carried out for a number of special cases. The validity of the suggested approach is verified by the numerical simulation results. © Pleiades Publishing, Ltd., 2011.

关键词： Circuit simulation

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Formation of IP-Core Libraries in the User IC design Flow for FPGAs and RSoCs

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Russian microelectronics 2022年第7期51卷 567-572页

作者： Khvatov, V.M. Gavrilov, S.V. Institute for Design Problems in Microelectronics of the Russian Academy of Sciences Moscow Russia

Abstract: Complex functional blocks or intellectual property (IP) cores are developed and used to speed up the user IC design flow and improve their final characteristics. There are two IP-cores types—soft IP-cores and hard IP-cores. A hard IP core has a fixed on-chip layout and pre-routed interconnects, while a soft IP core consists of logic gates and requires placement and routing. For an automated flow for designing ICs based on FPGAs and reconfigurable systems on a chip (RSoC) it is necessary to develop core libraries that allow them to be identified at each stage of the design flow. The paper shows various types and formats of libraries of soft and hard IP-cores used in the design flow for ICs based on FPGAs and Russian-made RSoCs. Methods for designing libraries of necessary CAD systems at the stages of logical synthesis, automatic technological mapping and layout synthesis are described. The characteristic features of soft and hard IP-cores libraries, as well as methods for their formation, are considered taking into account the architecture of FPGAs and RSoCs. The proposed design methods make it possible to develop libraries that are necessary for the automated implementation of all types of IP-cores, taking into account the advantages of the architecture of basic FPGAs and RSoCs. © 2022, Pleiades Publishing, Ltd.

关键词： Field programmable gate arrays (FPGA)

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Accurate Soft Error Rate Reduction using Modified Resolution Method

Accurate Soft Error Rate Reduction using Modified Resolution...

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2019 IEEE East-West design and Test Symposium, EWDTS 2019

作者： Stempkovskiy, Alexander Telpukhov, Dmitry Nadolenko, Vladislav Institute for Design Problems in Microelectronics Moscow Russia Department at Institute for Design Problems in Microelectronics Moscow Russia Design Engineer at Institute for Design Problems in Microelectronics Moscow Russia

ISBN: (纸本)9781728110035

The influence of cosmic radiation on integrated circuits is one of the most important reliability challenges of modern semiconductor technologies, and the most significant problems are associated with single event effects. Consequently, even at the early stage of the logical synthesis of combinational circuits, it is necessary to take into account the requirements for the reliability of operation. The article proposes an iterative method of resynthesis of combinational circuits by using implicit don't cares. The extraction procedure of these don't cares is performed using a modified resolution method, which has been widely used in the field of automated reasoning and especially in automated theorem proving. The applicability of the iterative process is ensured by effective metrics and methods for evaluating the reliability of combinational circuits. The proposed approach differs from the known methods in the absence of errors in finding logical constraints and accurate estimation of the soft error rate (SER) at each iteration. The effectiveness of the method is demonstrated on a large set of benchmark circuits. © 2019 IEEE.

关键词： Fault tolerance

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Boolean Satisfiability Methods for Modern Computer-Aided design problems in microelectronics

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Russian microelectronics 2021年第7期50卷 516-522页

作者： Zapletina, M.A. Zhukov, D.V. Gavrilov, S.V. Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124681 Russia

Abstract: The Boolean satisfiability (SAT) methods are one of the efficient approaches used to solve the problems of Boolean matching and the equivalence checking of digital circuits. In combination with classic routing algorithms and optimization techniques, these methods demonstrate better results than the classic routing algorithms in terms of the speed of operation and the quality of the results. In this paper, the modern practice of using the SAT methods in computer-aided design systems for VLSI is analyzed. The examples of modern SAT approaches to the problems of routing and the formal equivalence checking of digital circuits’ descriptions within the technological mapping as a part of the FPGA design flow are considered. The algorithm of the detailed routing of the FPGA switching blocks using the satisfiability problem is developed and presented. The results of its work are demonstrated on the example of the programmable logic block of the integrated circuit 5400TP094 made in Russia. The block has the island architecture, where the configurable logic blocks and switching blocks form a regularly repeated layout template. The properties of the chosen classic architecture allow us to expand the region of the presented algorithm to the entire class of island style of FPGA. The algorithm is tested on the project benchmarks ISCAS-85, ISCAS-89, and LGSynth-89. The comparison of the developed SAT-based algorithm with the well-known routing algorithm Pathfinder is presented by the criteria of the elapsed time and the achieved degree of routed nets in the switching blocks. It is specified that the considered Boolean satisfiability methods for the routing problem are capable to prove the circuit’s unroutability, unlike the Pathfinder algorithm whose results can only implicitly indicate it. The paper demonstrates that the application of a more efficient SAT solver significantly accelerates the work of the suggested detailed routing algorithm. © 2021, Pleiades Publishing,

关键词： Field programmable gate arrays (FPGA)

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Methods and Algorithms for the Logical-Topological design of Microelectronic Circuits at the Valve and Inter-Valve Levels for Promising Technologies with a Vertical Transistor Gate

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Russian microelectronics 2019年第3期48卷 167-175页

作者： Ivanova, G.A. Ryzhova, D.I. Gavrilov, S.V. Vasilyev, N.O. Stempkovskii, A.L. The Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124365 Russia

Abstract: The technological rules and design standards have become much more complicated with the increase in the degree of integration of microelectronic systems and the reduction of the technological dimensions of the basic elements to 32 nm and smaller. There are several thousand design restrictions for technologies with transistor sizes of 32 nm and smaller. Compliance with the full set of rules and design standards in the automatic mode becomes impossible when using the existing approaches to solving problems of logical and topological synthesis. This leads to the need for a large amount of manual work with the editing scheme and topology at the final stage of verification of the project as a whole. The transition to the use of regular structures in the lower layers of the topology has solved the problem of the increasing number of design standards for technologies of 22 nm and below. Methods and algorithms for the logical-topological design of microelectronic circuits at the valve and inter-valve level for advanced technologies with a vertical transistor gate have been proposed in this paper. The method of the inter-vent resynthesis of circuits taking into account the specific of designing circuits on Fin FET transistors is proposed. The proposed approach combines the methods of logical resynthesis and structural optimization of the circuit in order to achieve the required parameters (area, fault tolerance, or taking into account the design features of VLSI). An algorithm for combining the fragments of the topology of the standard cells and blocks that were obtained as a result of inter-valve resynthesis taking into account the specifics of designing circuits on FinFET transistors is proposed. © 2019, Pleiades Publishing, Ltd.

关键词： Topology

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Solving the FPGA Routing Problem Using the Model of an Extended Mixed Routing Graph

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Russian microelectronics 2023年第7期52卷 682-689页

作者： Zapletina, M.A. Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124365 Russia

Abstract: An architecture-aware extended mixed routing graph model allows describing the features of the routing resources of modern field-programmable gate arrays (FPGA). It can be used to solve the tasks of interconnections routing as part of an FPGA layout synthesis flow. In this work, an architecture-aware extended mixed routing graph model is considered. Two modifications are proposed for the basic method of automatic routing that is the classical Pathfinder algorithm adapted to a mixed routing resources graph. The first modification is based on the idea of a directed search on the graph model using data on the spatial and geometric characteristics of the basic FPGA chip, while the second one combines a directed search strategy with consideration of a preliminary routing congestion assessment based on the results of the placement procedure. It has been demonstrated that the proposed modifications make it possible to accelerate the basic method convergence by an average of 50.6 and 38.6%, respectively. While maintaining the routability of IWLS’2005, ISCAS’89 and LGSynth’89 benchmark suits, the use of only directed search led to an improvement in the timing characteristics of test circuits implementations by 5.2% on average, and its use together with an assessment of congestion before the start of routing, to these characteristics improvement by 9.3% on average relative to the results of the basic Pathfinder method. © Pleiades Publishing, Ltd. 2023. ISSN 1063-7397, Russian microelectronics, 2023, Vol. 52, No. 7, pp. 682–689. Pleiades Publishing, Ltd., 2023. Russian Text The Author(s), 2022, published in Izvestiya Vysshikh Uchebnykh Zavedenii, Elektronika, 2022, Vol. 27, No. 6, pp. 774–786.

关键词： Field programmable gate arrays (FPGA)

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Dynamics of the Vector of Magnetization in a Free Layer of a Spin Valve with Planar Anisotropy under the Action of Arbitrarily Directed Magnetic Fields

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Bulletin of the Russian Academy of Sciences: Physics 2023年第3期87卷 310-317页

作者： Iusipova, Iu. A. Skidanov, V.A. Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124365 Russia

Abstract: Modeling is done for the dynamics of the vector of magnetization in the free layer of a spin valve with planar layer anisotropy in arbitrarily directed magnetic fields. Bifurcation analysis of the dynamic system, the conditions for changing the type of singular points are established, and the dynamics of magnetization is classified. © 2023, Allerton Press, Inc.

关键词： Magnetization

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