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检索条件"机构=Institute for Design Problems in Microelectronics"

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Triple CJFET (Si, SiN, GaN, GaAs) Analog of the CMOS Transistor and its Main Connection Circuits in Lowerature Electronics

Triple CJFET (Si, SiN, GaN, GaAs) Analog of the CMOS Transis...

引用

2020 IEEE International Conference on Electrical Engineering and Photonics, EExPolytech 2020

作者： Prokopenko, Nikolay N. Zhuk, Alexey A. Ivanov, Yuri I. Don State Technical University Institute for Design Problems in Microelectronics of RAS Rostov-on-Don Zelenograd Russia Southern Federal University Rostov-on-Don Russia

ISBN: (纸本)9781728188782

The structure of the CJFET composite transistor (CT) for JFET technologies (Si, SiC, GaN, GaAs, etc.) is proposed, which in its drain-gate characteristics is similar to a CMOS junction field-effect transistor with an induced channel. The structure of the CJFET CT under consideration has a typical off state zone with a gate-source voltage not exceeding its threshold voltage. When the voltage increases at the equivalent gate, the CT switches to the active mode and can be used in tasks of analog signal amplification. Besides, with respect to the equivalent drain terminal of the CT, the signal is not inverted in the proposed CT. This is its wonderful feature. The main connection silicon circuits of the CT in cryogenic electronics are considered. © 2020 IEEE.

关键词： Gallium arsenide

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Backpass Trees for Modifying PathFinder-based Routing Algorithm for FPGA

Backpass Trees for Modifying PathFinder-based Routing Algori...

引用

IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering, SIBIRCON

作者： Alexander Y. Chistiakov Mariya A. Zapletina Sergey V. Gavrilov CAD Department Institute for Design Problems in Microelectronics of RAS Zelenograd Russia Administration Department Institute for Design Problems in Microelectronics of RAS Zelenograd Russia

ISBN: (纸本)9781665464819

In the field-programmable gate array and programmable system-on-a-chip design flow routing is a highly time-consuming stage that provides the last opportunity to make any design optimizations. Therefore, reducing its runtime with no significant losses in a quality of result occurs to be an extremely important problem to solve. This paper proposes a modification of a PathFinder-based algorithm to implement a directed search technique which contributes FPGA routing acceleration. The main idea is to direct the searching process by routing graph connectivity consideration in a form of backpass trees. The modification is relevant for the situation when there are no geometric coordinates known for FPGA/PSoC routing resources. The modified algorithm was tested on IWLS’2005 and some commercial benchmark sets. The obtained experimental results demonstrate an average runtime reduction by 10% while the average critical path delay and wirelength slightly increase (1.8% and 0.3% respectively) caused by usage of the introduced backpass trees structures.

关键词： Runtime design automation Forestry Benchmark testing Routing Delays System-on-chip

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Room Frequency Response Equalization Using Modified X-Filtered Adaptive Algorithms

Room Frequency Response Equalization Using Modified X-Filter...

引用

Siberian Conference on Control and Communications (SIBCON)

作者： Victor Djigan Institute for Design Problems in Microelectronics of RAS Moscow Russia

ISBN: (纸本)9781665476294

This article presents a technology of the acoustic frequency response equalization. It is based on the usage of the modified x-filtered adaptive algorithms in the equalizers. Comparing to the traditional x-filtered algorithms, the modified ones allow to accelerate the equalizer convergence if the computationally simple LMS or the NLMS adaptive algorithms based on the gradient search strategy are used for the equalizer weights computation. Besides, the modification allows to use the computationally complex but simultaneously efficient RLS adaptive algorithms in the x-filtered mode because the algorithms cannot be used in the traditional x-filtered mode. The proposed equalizer architectures and the computational procedures of the traditional and modified adaptive filtering algorithms are presented. Simulation demonstrates a better performance of the modified algorithms comparing to the traditional ones in the following terms: the equalized frequency response ripple value, the proximity of the PSD curves of the undistorted speech signal and the signal passed through the equalizer and acoustic medium, the initial duration of the transient response of the error signal and the response steady-state value.

关键词： Transient response Gradient methods Computational modeling Computer architecture Filtering algorithms Frequency response Acoustics

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Reduced Complexity Antenna Array Calibration Algorithm

Reduced Complexity Antenna Array Calibration Algorithm

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Digital Signal Processing and its Applications (DSPA), International Conference on

作者： Victor Djigan Institute for Design Problems in Microelectronics of RAS Moscow Russia

A phase-less algorithm of the antenna array calibration is presented in this paper. The algorithm is used to estimate and compensate the signal phase lag variation in the array channels. The estimated phase lags include the lags, caused by the channel equipment, and the lags, caused by the signal source spatial location in the case of the receiving array or, otherwise, the receiver spatial location in the case of the transmitting array. The compensation of the first-mentioned phase lags means the array calibration and the compensation of the second-mentioned phase lags means the array calibration and beam steering simultaneously, because the channel, space and phase lags are not separable. The proposed algorithm requires $\boldsymbol{4+4(M-1)}$ measurements of the array output power after the changing of the signal phase to the specific values sequentially in the pairs of the reference and each of the calibrated channels of the array. Here, $\boldsymbol{M}$ is the number of the array channels. This algorithm requires about 33% less power measurements, and therefore has less complexity comparing to the similar calibration algorithm, which requires $\boldsymbol{2+6(M-1)}$ of such measurements. The accuracy of the channel phase estimation using the proposed or known calibration algorithm does not exceed the value of one discrete of the phase quantization by means of the digitally controlled phaseshifter. The proposed algorithm can be used in arrays of arbitrary geometric configuration.

关键词： Phased arrays Antenna measurements Power measurement Phase measurement Array signal processing Signal processing algorithms Channel estimation

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The Analysis of Logic Resynthesis Methods to Increase the Fault Tolerance of Combinational Circuits for Single Failures

The Analysis of Logic Resynthesis Methods to Increase the Fa...

引用

IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

作者： Nikolay O. Vasilyev Mariya A. Zapletina Galina A. Ivanova Institute for Design Problems in Microelectronics of RAS Zelenograd Russia

ISBN: (数字)9781665404761

ISBN: (纸本)9781665446426

The paper discusses the methods for protecting logic elements of combinational circuits from single failures. Until recently, the problem of manufacturing the microelectronic products resistant to single failures of logic elements was relevant mainly in the military and space industries. In these areas, the increased requirements are imposed on the fault tolerance of circuits, since the latter are functioning under the influence of external destabilizing factors. These factors can be heavy charged particles that affect the operation of logic elements and cause their single failures. Due to the solid-state devices scaling, the technological standards for integral circuits design and manufacturing change and the fault tolerance problem becomes relevant for devices of the civilian market, also. The paper proposes a technique for a resynthesis of vulnerable areas of logic combinational circuits. To assess the stability, the logic constraints derived from the resolution method are suggested to use.

关键词： Fault tolerance Sensitivity Fault tolerant systems Stability criteria Combinational circuits Manufacturing Standards

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High-Speed Operational Amplifiers Based on the Advanced Derivatives of the Class AB Intermediate Stage 5

High-Speed Operational Amplifiers Based on the Advanced Deri...

引用

5th International Youth Conference on Radio Electronics, Electrical and Power Engineering, REEPE 2023

作者： Prokopenko, Nikolay Chumakov, Vladislav Kleimenkin, Dmitriy Don State Technical University Institute for Design Problems in Microelectronics of Ras Zelenograd Rostov-on-Don Russia Don State Technical University Rostov-on-Don Russia

ISBN: (纸本)9798350399523

In this paper, the circuitry of the AB class intermediate stage for fast-acting Op-Amps, including those on CMOS and arsenide-gallium transistors, which allows to significantly increase the SR of Op-Amos, is developed. The purpose and novelty of the present paper is to investigate new structures of intermediate stages (ISs), which complement known publications on problems of increasing the speed response of Op-Amps. To achieve the aim the drawbacks of a very popular in automation and measurement devices architecture of an operational amplifier (Op-Amp) with a IS based on a "folded"cascode have been considered. As an example, the paper gives one of them - a nonlinear mode of operation of the IS, which does not allow to provide a large current overcharge correction capacitor Op-Amp, which has a negative impact on the maximum rate of increase of the output voltage (SR). In conclusion of article, results of computer simulation of static modes and dependence of output currents of IS on input voltage in environment LTSpice are discussed, showing, that the relation of maximum output current of IS to its current in a static mode exceeds two orders, that has positive influence on SR. © 2023 IEEE.

关键词： Operational amplifiers

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Espresso-like Iterative Algorithm for Three-Level Logic Minimization

Espresso-like Iterative Algorithm for Three-Level Logic Mini...

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Networks, Circuits and Systems (NCS), Seminar on

作者： Alexander L. Stempkovsky Dmitry V. Telpukhov Vladislav V. Nadolenko Institute for Design Problems in Microelectronics of RAS Moscow Russia

Minimization is an important part of any logic synthesis algorithm. Espresso algorithm can be used as a first step for global two-level minimization. Then factorization is performed to obtain multi-level structure and various local optimization algorithms are applied. This paper presents a new algorithm called Xpresso to replace Espresso in described synthesis flow. It works with three-level logic circuit structure in a form of DNF with an extra layer of XORs. Such structure allows more compact representation than pure DNF while keeping global minimization feasible. Proposed minimization algorithm consists of three iterative Espresso-like steps: expand, irredundant and reduce, tweaked to work with three-level structure. Computational complexity stays mostly at original Espresso's level with most expensive part of expand being transferred to GPU. Experimental results are provided for combinational logic circuits from LGSynth'91 benchmark. Xpresso's outputs are compared to those of Espresso by operation count and a few other metrics.

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Method for Increasing Fast Response of the Operational Amplifiers in the Inverting Connection with an Input Stage of the Dual-Input-Stage Class and a Push-Pull 'Folded' Cascode

Method for Increasing Fast Response of the Operational Ampli...

引用

2022 International Conference on Electrical Engineering and Photonics, EExPolytech 2022

作者： Prokopenko, Nikolay Chumakov, Vladislav Klejmenkin, Dmitriy Don State Technical University Institute for Design Problems in Microelectronics of Ras Zelenograd Rostov-on-Don Russia Don State Technical University Rostov-on-Don Russia

ISBN: (数字)9781665490306

ISBN: (纸本)9781665490306

A new method for connecting differentiating correction circuits in the inverting connection of the high-speed operational amplifiers (Op-Amp) implemented on the basis of a push-pull 'folded' cascode is developed and studied. Forcing the processes of recharging an integrating balancing capacitor responsible for the formation of the logarithmic amplitude-frequency characteristic and ensuring the specified phase stability margin of the Op-Amp is provided in the suggested circuits. At the same time, the maximum slew rate increases significantly (by 10-100 times) up to 1000 V/μ s-2000V/μ s, The results of computer simulation of CMOS and BJT high-speed Op-Amps in the inverting drivers of the high-speed ADCs implemented on the input stages of the dual-input-stage class are presented. © 2022 IEEE.

关键词： Operational amplifiers

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Improving Pathfinder Algorithm Perfomance for FPGA Routing

Improving Pathfinder Algorithm Perfomance for FPGA Routing

引用

IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

作者： Mariya A. Zapletina Daniil A. Zheleznikov Sergey V. Gavrilov Institute for Design Problems in Microelectronics of RAS Zelenograd Russia

ISBN: (数字)9781665404761

ISBN: (纸本)9781665446426

The paper presents some algorithmic improvements to accelerate the routing stage for FPGA. One of the main advantages of FPGA is the high development speed; thereby the importance of efficient computer-aided design tools for modern FPGA is hard to overestimate. The placement and routing stages are crucial for the FPGA performance, and meanwhile they take up a significant part of the design time. The investigated base routing algorithm is the modified Pathfinder for the mixed routing resources graph. Pathfinder is a popular iterative negotiation-based router acting on the principle of eliminating nets congestions. Due to the proposed algorithmic improvements, such as ignoring the uncongested nets while rip-up and rerouting stage, and some other, the summary routing time is reduced significantly. The observed average time decrease is from 1.3X to 2.6X depending on the FPGA architecture. The benchmarks ISCAS'85&89, LGSynth'89 and several real industrial circuits were used for testing.

关键词： design automation Conferences Tools Logic gates Routing Acceleration Field programmable gate arrays

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Adaptive Antenna Array, Shared with Adaptive Equalizer : Invited Paper

Adaptive Antenna Array, Shared with Adaptive Equalizer : Inv...

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2020 IEEE Ukrainian Microwave Week (UkrMW)

作者： Victor Djigan Institute for Design Problems in Microelectronics of RAS Moscow Russia

ISBN: (数字)9781728173139

ISBN: (纸本)9781728173146

This paper considers an Adaptive Antenna Array (AAA), which weights are shared with those of a Feed-Forward (FF) part of the channel equalizer and the array output signal is combined with that of the Feed-Backward (FB) part of the equalizer. The array and this distributed equalizer operate as an indivisible adaptive filter, providing a good performance and an ability to receive a multipath data signal in the presence of external interference sources. The architecture of the array/equalizer and mathematical description of the Recursive Least Mean Squares (RLS), Least Mean Square (LMS) and Normalized LMS (NLMS) algorithms for weights calculation of the adaptive filter are presented. The simulation results demonstrate the efficiency of the proposed solution.

关键词： Equalizers Simulation Adaptive arrays Adaptive filters Interference Microwave antenna arrays Arrays

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