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Solving the problems of Routing Interconnects with a Resynthesis for Reconfigurable Systems on a Chip

Russian microelectronics 2018年第7期47卷 516-521页

作者： Gavrilov, S.V. Zheleznikov, D.A. Khvatov, V.M. Institute of Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia National Research University MIET Moscow Russia

Abstract: The existing means of design automation are focused mainly on the technology of foreign manufacturers, which makes it necessary to adapt the existing methods and means for designing reconfigurable systems-on-a-chip and to develop domestic specialized CAD tools to solve urgent problems in this field. Methods are proposed for solving interconnection routing problems in conjunction with logical resynthesis, applied to the architecture of a reconfigurable system-on-a-chip based on the domestic field-programmable gate array (FPGA) of the Almaz-14 family. Developers from JSC "NIIME" and PJSC "Micron" laid broad configurational solutions, which do not have foreign analogues, into this crystal. A wide range of additional elements for the configuration, as well as the potentialities for the logical resynthesis of the FPGA Almaz-14 chip, have led to the need to develop new methods for routing interconnections that would allow us to take into account and use these architectural features. An efficient algorithm for the automatic routing of interconnections for a reconfigurable system on a chip based on FPGAs belonging to the Almaz-14 family based on algorithm A* is developed. This algorithm represents a modification of the classical algorithm searching for the shortest path on a graph, the Dijkstra algorithm, including a mixed switching graph model. To describe the variety of additional switching elements, a special generalized mathematical model, as well as a special interface in the command language Tcl are developed, the latter includes a list of elements for configuration, as well as their description and functional purpose. This work has increased the efficiency of computer-aided design using programmed mechanisms developed and implemented in the C programming language for the optimal use of the configuration and routing elements of FPGAs, as well as mechanisms for the complete and entire routing of interconnections. © 2018, Pleiades Publishing, Ltd.

关键词： Computer aided design

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Layout Synthesis design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip

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Russian microelectronics 2019年第3期48卷 176-186页

作者： Gavrilov, S.V. Zheleznikov, D.A. Zapletina, M.A. Khvatov, V.M. Chochaev, R. Zh. Enns, V.I. Institute for Design Problems in Microelectronics Russian Academy of Sciences Zelenograd Moscow124365 Russia Zelenograd Moscow124460 Russia

Abstract: A layout synthesis design flow for implementing designs on reconfigurable systems-on-chip is developed by the institute for design problems in microelectronics of Russian Academy of Sciences, in cooperation with JSC "NIIME" for special-purpose circuits produced at PJSC "Mikron". The developed methodology includes new techniques to solve layout synthesis problems at different design flow stages, including the initial circuit decomposition, placement of logical elements, and the interconnections routing. Presented design flow makes it possible to accelerate the development of large IP blocks for reconfigurable systems-on-chip with multiple types of switching elements and system-on-chip components. © 2019, Pleiades Publishing, Ltd.

关键词： System-on-chip

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Automatic FPGA Placement Configuration for Customer designs

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Russian microelectronics 2022年第7期51卷 579-584页

作者： Enns, V.I. Gavrilov, S.V. Chochaev, R. Zh. Research Institute of Molecular Electronics Moscow124460 Russia Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124681 Russia

Abstract: Specialization of configurable heterogeneous ICs for specific customer proposals requires the flexibility of design and technological solutions. This, in turn, leads to the necessity of the automatic adjustment of CAD, including software placement tools, on the changes made. The development of efficient methods and tuning algorithms is impossible without relying on the appropriate mathematical apparatus. This study presents a set-theoretic mathematical model of a hierarchical project and formalizes a hierarchical approach to the netlist using the apparatus of set theory, mathematical logic, and graph theory. To ensure quick configuration of clustering and placement software tools, taking into account the changes made to the basic design, the correspondence between the elements of the basic FPGA design and user-designed circuits from the end user is formalized. The obtained results can serve as a base for the development of the efficient methods and algorithms for the automatic tuning of software clustering and placement tools. © 2022, Pleiades Publishing, Ltd.

关键词： Field programmable gate arrays (FPGA)

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The Acceleration Techniques for the Modified Pathfinder Routing Algorithm on an Island-Style FPGA

The Acceleration Techniques for the Modified Pathfinder Rout...

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2022 Conference of Russian Young Researchers in Electrical and Electronic Engineering, ElConRus 2022

作者： Zapletina, Mariya A. Zheleznikov, Daniil A. Institute for Design Problems in Microelectronics of Ras Electronic Design Automation Department Moscow Russia

ISBN: (纸本)9781665409933

The paper presents two techniques to speed up routing of user circuits within an island-style FPGA design flow. The basic algorithm is the modified Pathfinder that supports a mixed route graph representation of FPGA routing resources. The first technique reduces the number of rip-up and reroute iterations and allows decreasing routing time by 38% on average while increasing the critical path delay up to 10% only. The second technique utilizes the idea of directed pathfinding on a mixed route graph with known geometric coordinates of its vertices and edges. Various values of directed path search adjustment factor were investigated and the optimal one was discovered. The introduced routing method adjusted by an optimal factor value is shown to double a routing speedup without routability degradation. Also, the paper proposes a formal description of FPGA routing resources and a routing task itself. © 2022 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Antenna Array Calibration Algorithm without Access to Channel Signals

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Radioelectronics and Communications Systems 2020年第1期63卷 1-14页

作者： Djigan, Victor I. Kurganov, Vladislav V. Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia National Research University of Electronic Technology Moscow Russia

This paper describes the algorithm of antenna array (AA) calibration, which estimates and compensates phase lags, caused by non-identical electrical characteristics of array channels. The algorithm does not require the access to the channel signals or the channels disabling. It uses only the array output power measurements under the specific channel phase perturbations. The algorithm accuracy equals the phase shifter quantization step, i.e. it is twice less than phase shifter accuracy itself and does not depend on the number of array channels. The algorithm accuracy is compared with two similar calibration algorithms, known from publications. The compared algorithms accuracy depends on the number of array channels and is much less than the proposed algorithm. Thus, the new algorithm can be widely used for the efficient AA calibration, signal source angular position estimation and tracking by a calibrated or a non-calibrated AA with any aperture shape: linear, flat or conformal, with an arbitrary distance between neighbor AA elements and with an arbitrary antenna selected as a reference one. © 2020, Allerton Press, Inc.

关键词： Phase shifters

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Pathfinder Algorithm Modification for FPGA Routing Stage

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Russian microelectronics 2022年第7期51卷 573-578页

作者： Zapletina, M.A. Gavrilov, S.V. Institute for Design Problems in Microelectronics of the Russian Academy of Sciences Moscow Russia National Research University of Electronic Technology Moscow Russia

Abstract: One of the main advantages of FPGA design flow is the high development speed;therefore, the importance of effective computer-aided design tools for modern microcircuits of these classes cannot be overestimated. Placement and routing are the most time-consuming stages of FPGA design flow. The quality of results of these stages is crucial to the final performance of custom digital circuits implemented on FPGA. The paper discusses an approach to accelerating the routing stage within the layout synthesis flow for FPGA by introducing a few algorithmic improvements to a routing procedure. The basic routing algorithm under study is a modified Pathfinder for a mixed routing resources graph. Pathfinder is a well-known negotiation-based routing algorithm that works on the principle of iteratively eliminating congestions of chip routing resources. The sets of test digital circuits ISCAS’85, ISCAS’89, LGSynth’89 and several custom industrial projects were used for computational experiments. The impact of the proposed algorithmic improvements was analyzed using four FPGA architectures. It has been established that due to the improvements of the algorithm proposed in the paper, the average reduction in routing time was from 1.3 to 2.6 times, depending on the FPGA architecture, with no significant negative effect on the timing characteristics of the designed circuits. © 2022, Pleiades Publishing, Ltd.

关键词： Field programmable gate arrays (FPGA)

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Synthesis of a Concurrent Error Detection Circuit Based on the Spectral R-Code with the Partitioning of Outputs into Groups

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Russian microelectronics 2019年第4期48卷 240-249页

作者： Stempkovskii, A.L. Tel’pukhov, D.V. Zhukova, T.D. Demeneva, A.I. Nadolenko, V.V. Gurov, S.I. Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124365 Russia Moscow State University Moscow119991 Russia

Abstract—: The pace of development of the microelectronic industry and the progress in the development of computer-aided design tools make problems associated with the development of combinational circuits that are resistant to short self-clearing faults relevant again. These faults occur due to a combination of many different factors, such as extreme operating conditions and transition to nanometer design standards. Structural redundancy methods are often used to solve this problem by the principles of the noiseless coding theory to protect information during its transmission over communication channels. However, these methods have a significant drawback, i.e., large structural redundancy. In this paper, we propose to use an approach based on the synthesis of fault-tolerant combinational circuits based on the spectral R-code to solve the problem of developing fault tolerant combinational circuits. If a specific part of the coder is protected using special technological means, this code can correct a single-bit error and detect a double-bit error. The resulting circuit has less structural redundancy compared to the traditional method of triple modular redundancy (TMR). An approach is also proposed based on partitioning circuit outputs into groups followed by synthesizing fault-tolerant combinational circuits based on the R-code, which increases the probability of error detection/correction, to minimize the probability of multiple-bit errors within a combinational circuit. The paper presents the results of a series of numerical experiments that show the efficiency of the proposed approaches. © 2019, Pleiades Publishing, Ltd.

关键词： Fault tolerance

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Debugging and testing features of the dataflow parallel computing system components and devices

Debugging and testing features of the dataflow parallel comp...

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2011 9th East-West design and Test Symposium, EWDTS'2011

作者： Levchenko, N.N. Okunev, A.S. Yakhontov, D.E. Zmejev, D.N. Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia

The paper describes the new tools for dynamic display of the computational process for modeling a dataflow parallel computing system that implements non-traditional architecture. These tools allow evaluating the effec... 详细信息

ISBN: (纸本)9781457719578

关键词： Parallel processing systems

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Organization of pipeline operations in mapping unit of the dataflow parallel computing system

Organization of pipeline operations in mapping unit of the d...

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2011 9th East-West design and Test Symposium, EWDTS'2011

作者： Levchenko, N.N. Okunev, A.S. Yakhontov, D.E. Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9781457719578

The paper reviews the architecture of dataflow parallel computing system, describes the operation mechanisms of one of the main system modules - the mapping unit. The pipeline mode of mapping unit is considered;an increasing of the capacity associated with the introduction of the pipeline is estimated. The process of step-by-step optimization of pipeline with a description of the bottlenecks and ways to bypass them is shown. © 2011 IEEE.

关键词： Pipelines

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Methods for Reducing the Number of Matching Operations in the Content-Addressable Memory of the Parallel Dataflow Computing System 'Buran' 3

Methods for Reducing the Number of Matching Operations in th...

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3rd IEEE International Conference on problems of Informatics, Electronics and Radio Engineering, PIERE 2024

作者： Levchenko, Nickolay N. Zmejev, Dmitry N. Klimov, Arkadiy V. Nrc 'Kurchatov institute' Department for Design Problems in Microelectronics Moscow Russia

ISBN: (纸本)9798331516321

The paper describes the dataflow computing model and the architecture of the parallel dataflow computing system implementing it. This computing model and architecture are one of the approaches to solving the problem of increasing the real performance of computing systems. The paper describes the principles of operation of hardware content-addressable memory, which most effectively implements the principles of the dataflow computing model. One of the important problems with such memory is its high power consumption during matching operations. Methods for reducing the number of matching operations and the number of compared bits (bits involved in the matching process) are proposed. Methods for reducing the number of matching operations aim to reduce 'parasitic' comparisons of bits and keys in the token matching process. The studies conducted on the behavioral block-register model of the system and the emulator of the system confirmed the applicability of these methods to reduce the number of bits compared when executing dataflow programs. © 2024 IEEE.

关键词： content-addressable memory dataflow computing model matching operations parallel dataflow computing system parasitic matchings

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