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Method for Increasing Fast Response of the Operational Amplifiers in the Inverting Connection with an Input Stage of the Dual-Input-Stage Class and a Push-Pull 'Folded' Cascode

Method for Increasing Fast Response of the Operational Ampli...

引用

2022 International Conference on Electrical Engineering and Photonics, EExPolytech 2022

作者： Prokopenko, Nikolay Chumakov, Vladislav Klejmenkin, Dmitriy Don State Technical University Institute for Design Problems in Microelectronics of Ras Zelenograd Rostov-on-Don Russia Don State Technical University Rostov-on-Don Russia

ISBN: (数字)9781665490306

ISBN: (纸本)9781665490306

A new method for connecting differentiating correction circuits in the inverting connection of the high-speed operational amplifiers (Op-Amp) implemented on the basis of a push-pull 'folded' cascode is developed and studied. Forcing the processes of recharging an integrating balancing capacitor responsible for the formation of the logarithmic amplitude-frequency characteristic and ensuring the specified phase stability margin of the Op-Amp is provided in the suggested circuits. At the same time, the maximum slew rate increases significantly (by 10-100 times) up to 1000 V/μ s-2000V/μ s, The results of computer simulation of CMOS and BJT high-speed Op-Amps in the inverting drivers of the high-speed ADCs implemented on the input stages of the dual-input-stage class are presented. © 2022 IEEE.

关键词： Operational amplifiers

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Improving Pathfinder Algorithm Perfomance for FPGA Routing

Improving Pathfinder Algorithm Perfomance for FPGA Routing

引用

IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

作者： Mariya A. Zapletina Daniil A. Zheleznikov Sergey V. Gavrilov Institute for Design Problems in Microelectronics of RAS Zelenograd Russia

ISBN: (数字)9781665404761

ISBN: (纸本)9781665446426

The paper presents some algorithmic improvements to accelerate the routing stage for FPGA. One of the main advantages of FPGA is the high development speed; thereby the importance of efficient computer-aided design tools for modern FPGA is hard to overestimate. The placement and routing stages are crucial for the FPGA performance, and meanwhile they take up a significant part of the design time. The investigated base routing algorithm is the modified Pathfinder for the mixed routing resources graph. Pathfinder is a popular iterative negotiation-based router acting on the principle of eliminating nets congestions. Due to the proposed algorithmic improvements, such as ignoring the uncongested nets while rip-up and rerouting stage, and some other, the summary routing time is reduced significantly. The observed average time decrease is from 1.3X to 2.6X depending on the FPGA architecture. The benchmarks ISCAS'85&89, LGSynth'89 and several real industrial circuits were used for testing.

关键词： design automation Conferences Tools Logic gates Routing Acceleration Field programmable gate arrays

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Espresso-like Iterative Algorithm for Three-Level Logic Minimization

Espresso-like Iterative Algorithm for Three-Level Logic Mini...

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Networks, Circuits and Systems (NCS), Seminar on

作者： Alexander L. Stempkovsky Dmitry V. Telpukhov Vladislav V. Nadolenko Institute for Design Problems in Microelectronics of RAS Moscow Russia

Minimization is an important part of any logic synthesis algorithm. Espresso algorithm can be used as a first step for global two-level minimization. Then factorization is performed to obtain multi-level structure and various local optimization algorithms are applied. This paper presents a new algorithm called Xpresso to replace Espresso in described synthesis flow. It works with three-level logic circuit structure in a form of DNF with an extra layer of XORs. Such structure allows more compact representation than pure DNF while keeping global minimization feasible. Proposed minimization algorithm consists of three iterative Espresso-like steps: expand, irredundant and reduce, tweaked to work with three-level structure. Computational complexity stays mostly at original Espresso's level with most expensive part of expand being transferred to GPU. Experimental results are provided for combinational logic circuits from LGSynth'91 benchmark. Xpresso's outputs are compared to those of Espresso by operation count and a few other metrics.

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Adaptive Antenna Array, Shared with Adaptive Equalizer : Invited Paper

Adaptive Antenna Array, Shared with Adaptive Equalizer : Inv...

引用

2020 IEEE Ukrainian Microwave Week (UkrMW)

作者： Victor Djigan Institute for Design Problems in Microelectronics of RAS Moscow Russia

ISBN: (数字)9781728173139

ISBN: (纸本)9781728173146

This paper considers an Adaptive Antenna Array (AAA), which weights are shared with those of a Feed-Forward (FF) part of the channel equalizer and the array output signal is combined with that of the Feed-Backward (FB) part of the equalizer. The array and this distributed equalizer operate as an indivisible adaptive filter, providing a good performance and an ability to receive a multipath data signal in the presence of external interference sources. The architecture of the array/equalizer and mathematical description of the Recursive Least Mean Squares (RLS), Least Mean Square (LMS) and Normalized LMS (NLMS) algorithms for weights calculation of the adaptive filter are presented. The simulation results demonstrate the efficiency of the proposed solution.

关键词： Equalizers Simulation Adaptive arrays Adaptive filters Interference Microwave antenna arrays Arrays

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High-Speed Operational Amplifiers Based on the Advanced Derivatives of the Class AB Intermediate Stage 5

High-Speed Operational Amplifiers Based on the Advanced Deri...

引用

5th International Youth Conference on Radio Electronics, Electrical and Power Engineering, REEPE 2023

作者： Prokopenko, Nikolay Chumakov, Vladislav Kleimenkin, Dmitriy Don State Technical University Institute for Design Problems in Microelectronics of Ras Zelenograd Rostov-on-Don Russia Don State Technical University Rostov-on-Don Russia

ISBN: (纸本)9798350399523

In this paper, the circuitry of the AB class intermediate stage for fast-acting Op-Amps, including those on CMOS and arsenide-gallium transistors, which allows to significantly increase the SR of Op-Amos, is developed. The purpose and novelty of the present paper is to investigate new structures of intermediate stages (ISs), which complement known publications on problems of increasing the speed response of Op-Amps. To achieve the aim the drawbacks of a very popular in automation and measurement devices architecture of an operational amplifier (Op-Amp) with a IS based on a "folded"cascode have been considered. As an example, the paper gives one of them - a nonlinear mode of operation of the IS, which does not allow to provide a large current overcharge correction capacitor Op-Amp, which has a negative impact on the maximum rate of increase of the output voltage (SR). In conclusion of article, results of computer simulation of static modes and dependence of output currents of IS on input voltage in environment LTSpice are discussed, showing, that the relation of maximum output current of IS to its current in a static mode exceeds two orders, that has positive influence on SR. © 2023 IEEE.

关键词： Operational amplifiers

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The Global Interconnect Routing Approach for Reconfigurable System-on-a-Chip

The Global Interconnect Routing Approach for Reconfigurable ...

引用

IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

作者： Mariya A. Zapletina Daniil A. Zheleznikov Sergey V. Gavrilov Institute for Design Problems in Microelectronics RAS (IPPM RAS) Moscow Russia

ISBN: (数字)9781728157610

ISBN: (纸本)9781728157627

The paper considers a global stage of the hierarchical approach to the interconnect routing for island-style reconfigurable system-on-a-chip. The presented technique can also be applied to the programmable integrated circuits and systems-on-a-chip with the switching blocks included. The approach is based on two fundamentals. The first is the use of the modified PathFinder algorithm for both the global and detailed switching blocks level routing. The second is the construction of the mixed route graph assuming the switching blocks are the "black boxes" with a description of the legal inputs-to-outputs connections for the global level routing. Much attention is paid to the rules of a local graph model of switching blocks and their functional parameterized description in Tcl. The presented methods are demonstrated for the case of two types of switching blocks. The computational experiments results in the CPU time for a flat routing and the hierarchical approach routing time in comparison.

关键词： Routing Switches Integrated circuit interconnections Switching circuits Task analysis System-on-chip microelectronics

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The Review of Cellular Automata Algorithms for Placement and Routing problems

The Review of Cellular Automata Algorithms for Placement and...

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IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

作者： Mariya A. Zapletina Denis V. Zhukov Institute for Design Problems in Microelectronics of RAS Zelenograd Russia

ISBN: (数字)9781665404761

ISBN: (纸本)9781665446426

The paper proposes a review of the modern research experience of the cellular automata algorithms, models and methods to solve the problem of searching the shortest paths and the placement task for the logic elements within the design flow for FPGA. The classical and hybrid cellular automata models are considered. The particular attention is paid to the cellular automata with multi-agent semantics for the shortest path search algorithms. A detailed analysis of the model for solving the placement problem based on the systolic structure is given. The main difficulties and possible problems of the cellular automata models and algorithms for placement and routing stages of an FPGA design flow are highlighted and discussed.

关键词： Semantics Automata Logic gates Search problems Routing Task analysis Field programmable gate arrays

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Least Squares Criterion Adaptive Filtering Algorithms as Tools for Calibration of Arrays with Digital Beamforming

Least Squares Criterion Adaptive Filtering Algorithms as Too...

引用

2020 IEEE Ukrainian Microwave Week (UkrMW)

作者： Victor Djigan Vladislav Kurganov Institute for Design Problems in Microelectronics of RAS Moscow Russia

ISBN: (数字)9781728173139

ISBN: (纸本)9781728173146

This paper explores the application of the adaptive filtering algorithms, based on Least Squares (LS) criterion for the calibration of the receiving arrays with digital beamforming. The digital beamforming assumes the access to the signals in the array channels as a requirement, which has to be provided if the adaptive signal processing is used. In this case, the adaptive filtering algorithms, based on the minimization of the LS error between the desired and array output signals, are able to estimate the channel parameter spread, which values can be stored and used for correction of the array weights during the beam steering. If a set of steered beam positions is known, for example in scanning arrays, the proposed algorithm allows to create a codebook of the array weights, which ensures the random variation of channel's parameters compensation and correct beam steering. The architecture of the proposed solution and mathematical description of a Recursive Least Squares (RLS) adaptive filtering algorithm, on which the calibration is based on, are presented. The algorithm uses a dynamic regularization of the array input signal correlation matrix. No specific correlation properties are required for the algorithm training signal. The simulation results demonstrate the ability of the calibration algorithm to compensate the channel's parameters spread. If the array channel Signal-to-Noise Ratio (SNR) is 0 ... 30 dB, then the achieved spread of the calibrated channels gain errors is about -20 dB. The norm of the ideal and calibrated array difference is also about -20 dB. The results are obtained with the Phase Shift Keying (PSK) and Quadrature Amplitude Modulated (QAM) training signals. The ability of the proposed calibration algorithm to operate in interference conditions is also demonstrated.

关键词： Training Array signal processing Heuristic algorithms Signal processing algorithms Adaptive arrays Filtering algorithms Calibration

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Low Complexity RLS Adaptive Filters

Low Complexity RLS Adaptive Filters

引用

Digital Signal Processing and its Applications (DSPA), International Conference on

作者： Victor Djigan Institute for Design Problems in Microelectronics of RAS Moscow Russia

This paper presents two adaptive filters with a reduced arithmetic complexity which are based on the Recursive Least Squares (RLS) algorithms. The first one is the cascaded adaptive filter. The second one is the adaptive filter with the diagonalized correlation matrix of the input signal. The both filters have a reduced arithmetic complexity comparing to the direct implementation of the adaptive filter. The cost of the reduction is some degradation of the adaptive filter performance. The reduction is achieved only if the RLS algorithms with quadratic complexity are used. The computational procedures and the arithmetic complexities of the considered adaptive filters are the same, but the performance is different. This paper presents the RLS algorithms based on the Matrix Inversion Lemma (MIL). However, all the results and conclusions are valid for any RLS algorithms with quadratic complexity. The paper demonstrates the considered adaptive filter performance via simulation.

关键词： Degradation Adaptation models Costs Correlation Adaptive filters Signal processing algorithms Digital signal processing

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Antenna Array Calibration Algorithm Based on Phase Perturbation

Antenna Array Calibration Algorithm Based on Phase Perturbat...

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2019 IEEE East-West design and Test Symposium, EWDTS 2019

作者： Djigan, Victor Kurganov, Vladislav Institute for Design Problems in Microelectronics of RAS National Research University of Electronic Technology Moscow Russia Institute of Microdevices and Control Systems National Research University of Electronic Technology Moscow Russia

ISBN: (纸本)9781728110035

The paper presents an algorithm of antenna array calibration, which estimates and compensates phase lags, caused by non-identical electrical characteristics of the array channels. To estimate the phase lags, the algorithm uses only the array output power measurements under the specific channel phase perturbations. The estimation accuracy equals phase shifter quantization step and does not depend on the number of the array channels. The algorithm is compared with two similar calibration algorithms, known from publications, whose accuracy depends on the number of the array channels and is much less compared with that of the proposed algorithm. For this reason, the algorithm, presented in this paper, can be widely used for efficient arrays calibration, signal source angular position estimation and tracking by a calibrated or a non-calibrated array with any aperture shape: linear, flat or conformal and with an arbitrary channel, selected as a reference one. © 2019 IEEE.

关键词： Calibration

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