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检索条件"机构=Institute for Design Problems in Microelectronics of RAS"

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Prospects for Development of Fast Recovery Power GaAs SBD on the basis of LPE-Technology

Prospects for Development of Fast Recovery Power GaAs SBD on...

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2019 International Seminar on Electron Devices design and Production, SED 2019

作者： Voitovich, Victor E. Gordeev, Alexander I. Prokopenko, Nikolay N. Bugakova, Anna V. Intelsob LLC Ulyanovsk Russia Institute for Design Problems in Microelectronics of RAS Don State Technical University Rostov-on-Don Zelenograd Russia DSTU Rostov-on-Don Russia

ISBN: (纸本)9781538665244

The article is devoted to advanced high voltage, high temperature and hyperfast GaAs SBD, GaAs HJSBD structures with extreme high electrical and physical characteristics (VRRM = 1200 V;IF = 10 ÷ 50 A;VF ≤ 0.5 V;τrr=5÷10 ns;maximum junction temperature Tj = 300°C;Tcase = 250°C;fsw = 5÷8 MHz). We have compared the suggested diodes with high current SiC, GaAs and Si diodes, produced by microelectronics leaders. A brief description of LPE-process is given. We have shown that a specific feature of the suggested epitaxial structures is the existence of built-in quantum point magnetic centers with density 1013÷1014sm-3 in n--type epitaxial layer leading to sharp decrease of electron capture cross-section during diode reverse resistance recovery. The experiments have proved that this physical phenomenon is associated with drift electron capture cross-section change, that is equivalent to abrupt 'above-Gunn' increase of electrons' mobility. The experimental investigations have demonstrated, that LPE GaAs SBDs of classical variant of construction design have τrr ≈ 100 ps at operating voltages of 220 V. The possibility to decrease a direct fall of voltage at GaAs SBD (HJSBD) with simultaneous decrease of its barrier capacitance is under discussion. © 2019 IEEE.

关键词： Silicon carbide

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The Iterative SAT Based Approach to Detailed Routing for Reconfigurable System-on-a-Chip

The Iterative SAT Based Approach to Detailed Routing for Rec...

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IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

作者： Denis V. Zhukov Daniil A. Zheleznikov Mariya A. Zapletina Institute for Design Problems in Microelectronics RAS (IPPM RAS) Zelenograd Moscow Russia

ISBN: (数字)9781728157610

ISBN: (纸本)9781728157627

The paper presents a new iterative Boolean satisfiability (SAT) based approach to the routing of the switch blocks in an island-style reconfigurable system-on-a-chip. The detailed routing procedure results in obtaining the optimal combination of switches, multiplexors or tri-state buffers, inside a switch block. All the assigned interconnections should be completely routed without any conflicts. Within the SAT based approach each actually used switch block is presented as a Boolean equation system that is processed by the SAT-solver. In this paper the detailed routing task is solved for the switch blocks of two architectures. Their main difference is the quantity of tracks the current pin of switch block can be connected to. The computational experiments prove the efficiency of the considered method. The algorithm implemented in C programming language meets the requirements of the netlist full routability and minimization of routing runtime.

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Development of a Method for Timing Analysis of Reconfigurable System-on-a-Chip Based on Models of Special Logic Elements

Development of a Method for Timing Analysis of Reconfigurabl...

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IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

作者： Dmitry V. Telpukhov Roman A. Solovyev Vladimir S. Rukhlov Vasilii M. Khvatov Artem S. Mikhmel Institute for Design Problems in Microelectronics RAS (IPPM RAS) Zelenograd Moscow Russia

ISBN: (数字)9781728157610

ISBN: (纸本)9781728157627

In this paper, we propose methods for the timing analysis of circuits implemented in the basis of Reconfigurable System on a Chip (RSoC). The methods are based on the idea of clustering and partial characterization with the subsequent use of static timing analysis tools. RSoC refers to the new VLSI architecture, which contains FPGA-based reconfigurable logic blocks and IP cores, such as RAM, PLL, arithmetic blocks, and others. Partial characterization of a single cell takes time significantly less than the time of usual simulating the entire circuit in an electric simulator. The paper proposes methods of automatic parallelization of the computational process to further accelerate the timing analysis. The experiments demonstrate high accuracy in calculating the time delays of the circuit for an acceptable time, which makes it possible to use it in the task of finding the optimal place and route solution.

关键词： Macrocell networks Routing Timing Field programmable gate arrays Computer architecture Libraries Switches

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Dynamic Errors of Butterworth Band-Pass Filters in Analog-digital Control and Monitoring Systems

Dynamic Errors of Butterworth Band-Pass Filters in Analog-di...

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2022 International Russian Automation Conference, RusAutoCon 2022

作者： Samoylov, Leontiy Prokopenko, Nikolay Denisenko, Darya Southern Federal University Taganrog Russia Institute for Design Problems in Microelectronics of Ras Russia Don State Technical University Southern Federal University Taganrog Rostov-on-Don Russia

ISBN: (数字)9781665466554

ISBN: (纸本)9781665466554

The mathrm{n}{text{th}} order band-pass filters (BPF) included at the input of the analog-to-digital conversion (ADC) in the control and monitoring system (CMS) to extract a preset signal spectrum, consisting of the series-connected Butterworth n{text{th}} order low-pass filters (LPF) with a cutoff frequency of the amplitude-frequency characteristics (AFCs) and Butterworth n{text{-th}} order high-pass filters (HPF) with a cutoff frequency of the AFCs of the filter omega-{ss} are considered. Shows that the dynamic errors of the n{text{-th}} order BPFs are determined by the dynamic error of the n{text{-th}} order LPF with the cutoff frequency omega-{sH}, as well as the frequency ratio omega-{mathrm{ss}}/omega-{mathrm{sH}}. During the simulation, the delay times of signals in the BPF are obtained which makes it possible to determine the BPF dynamic error when changing the filter order for n=1,2,3 and estimate the dynamic error due to the information delay in the BPF. It has been established that for the filters under consideration there is an exponential dependence (negative exponent) of the value of the maximum dynamic error on the ratio omega-{mathrm{ss}}/omega-{mathrm{sH}}, which makes it possible to obtain a simple approximating analytical equation for the value of the dynamic error of the random order BPF. An estimation of the error of the proposed approximation is given. © 2022 IEEE.

关键词： Bandpass filters

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Temperature effects on the magnetoimpedance in glass-coated amorphous wires

Temperature effects on the magnetoimpedance in glass-coated ...

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2017 IEEE International Magnetics Conference, INTERMAG 2017

作者： Dzhumazoda, A. Panina, L.V. Morchenko, A.T. Adam, A. Awale, R. Podgornaya, S.V. National University of Science and Technology MISiS Moscow Russia Institute for Design Problems in Microelectronics RAS Moscow Russia Physics Department Faculty of Science Sohag University Sohag Egypt

ISBN: (纸本)9781538610862

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Low Pass Filter of the Sallen-Key Family with Main Parameters' Independent Adjustment 16

Low Pass Filter of the Sallen-Key Family with Main Parameter...

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16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Denisenko, Darya Prokopenko, Nikolay Bugakova, Anna South Federal University Rostov-on-Don Russia Don State Technical University Rostov-on-Don Russia Institute for Design Problems in Microelectronics of Ras Zelenograd Rostov-on-Don Russia

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

The new low pass filter's circuit (LPF) of the Sallen-Key family of the second order is considered, in which an main parameters' independent adjustment by digital-controlled resistors is realized: pole frequency, the quality factor and the scale transfer coefficient. The basic mathematical equations for the transfer function of the low pass filter are obtained. The comparison of the parameters of the known and proposed circuits is given. The results of LPF modeling in the Micro-Cap SPICE simulator are discussed. © 2022 IEEE.

关键词： Low pass filters

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Basic Parameters and Characteristics of the Op-Amp Based on the BiJFet Array Chip MH2XA030 Intended for the design of Radiation-Hardened and Cryogenic Analog ICs 14

Basic Parameters and Characteristics of the Op-Amp Based on ...

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14th International Scientific-Technical Conference on Actual problems of Electronic Instrument Engineering, APEIE 2018

作者： Dvornikov, Oleg V. Dziatlau, Valentin L. Tchekhovski, Vladimir A. Prokopenko, Nikolai N. Bugakova, Anna V. JSC 'Minsk Scientific and Research Instrument-Making Institute' Minsk Belarus Research Institute for Nuclear Problems Belarusian State University Minsk Belarus Don State Technical University Rostov-on-Don Russia Institute for Design Problems in Microelectronics RAS Zelenograd Russia

ISBN: (纸本)9781538670545

Features of the schematic design of two types of operational amplifiers (Op-Amp) on the new BiJFet array chip (AC) MH2XA030 are considered. The topology, the electric circuits of the Op-Amp and the results of their computer simulation are given. The brief information about the AC MH2XA030, intended for the accelerated creation of analog integrated circuits (IC) of automation devices, which retain their operational integrity under the influence of penetrating radiation and extremely low temperatures (up to -197°C) is presented. © 2018 IEEE.

关键词： Operational amplifiers

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Appraisal of the Effective Number of Bits of the ADC for Sensors with Account for Dynamic Errors

Appraisal of the Effective Number of Bits of the ADC for Sen...

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2020 IEEE East-West design and Test Symposium, EWDTS 2020

作者： Samoilov, Leonty Denisenko, Darya Prokopenko, Nikolay Southern Federal University Don State Technical University Rostov-on-Don Russia Don State Technical University Institute for Design Problems in Microelectronics of Ras Rostov-on-Don Zelenograd Russia

ISBN: (纸本)9781728198996

The static maximum relative error of the ADC for sensors is determined by the value of its least significant bit. During the input signal conversion in the ADC the information delay causes the dynamic error, which is added to the static error and actually reduces the effective number of bits. This decrease can be estimated by the effective number of bits, which illustrates the qualitative and quantitative assessment of the additional error. The article demonstrates that the effective bits rate is defined by the delay period of information in the ADC, as well as the sampling rate of the input signal. This, in turn, requires setting the spectrographic density (SD) for the converted signal, as well as an algorithm for selecting the sampling rate. It is recommended that the delay time of the ADC includes the delay in the analog storage and amplitude multiplexer, which are located at the ADC input and are directly involved in the conversion process. The article draws attention to the fact that the real sampling rate of analog signals, chosen from the point of view of the straight task of errors distribution in the automatic control system, significantly exceeds the sampling rate according to the sampling theorem. This requires the correction of the obtained results using the sampling theorem, in the direction of reduction of effective number of bits. © 2020 IEEE.

关键词： Analog storage

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Comparison of Fast Response and Noise of Charge-Sensitive Amplifiers with Various Types of Input Fets

Comparison of Fast Response and Noise of Charge-Sensitive Am...

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2020 International Symposium on Industrial Electronics and Applications, INDEL 2020

作者： Dvornikov, Oleg V. Tchekhovski, Vladimir A. Prokopenko, Nikolay N. Titov, Alexey E. Minsk Belarus Minsk Belarus Institute for Design Problems in Microelectronics of Ras Don State Technical University Rostov-on-Don Zelenograd Russia South Federal University Rostov-on-Don Russia

ISBN: (纸本)9781728198637

The circuit simulation results of the charge-sensitive amplifiers (CSA) with various types of input field-effect transistors (FET) are considered. CSA-1 and CSA-2 are implemented on Si bipolar transistors, besides in CSA-1 the input transistor is a Si field-effect transistor with p-n junction (Junction Field Effect Transistor, JFET) and in CSA-2- A GaAs FET with a gate formed by Schottky contact (metalized semiconductor FET, MESFET). CSA-3 is developed completely on the GaAs MESFET. In order to adequately compare the CSAs with respect to the rise-time t of the output pulses and the equivalent noise charge (ENC), all input transistors were selected with approximately equal drain current and the ratio of the gate width to the length W/L. The electrical circuits of the CSAs, the simulation results of the operating mode, the critical parameters, the dependence of t and the ENC on the capacity of the input signal source CD are presented. © 2020 IEEE.

关键词： Timing circuits

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Calculation of stress probability for NBTI-aware timing analysis

Calculation of stress probability for NBTI-aware timing anal...

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IEEE International Symposium on Quality Electronic design

作者： Alexander Stempkovsky Alexey Glebov Sergey Gavrilov Research Institute of Design Problems in Microelectronics IPPM RAS Moscow Russia

Negative bias temperature instability (NBTI) has become a primary mechanism that degrades performance of integrated circuits. It is well known that NBTI impacts pMOS transistors during circuit operation, and the degradation occurs when pMOS transistor is in a conducting state. So, accurate NBTI degradation analysis requires analysis of logic states. Degradation of specific pMOS transistor depends on part of lifetime, in which this transistor is under stress, in other words, on stress probability. In this paper, we propose the correct algorithm of calculating stress probability for every pMOS transistor of complex CMOS gate. Comparing to simple "naive" approach, our algorithm takes into account two additional factors: correlations between signals at gate inputs, and VDD-potential coming through "bottom" of pMOS transistor. Numerical experiments show the importance of accounting for both these factors.

关键词： Stress Probability Timing Degradation Niobium compounds Titanium compounds MOSFETs Circuits MOS devices Negative bias temperature instability

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