检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

161 篇 会议
15 篇 期刊文献

馆藏范围

176 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

73 篇 工学
- 54 篇 电子科学与技术（可...
- 33 篇 电气工程
- 23 篇 信息与通信工程
- 22 篇 计算机科学与技术...
- 14 篇 软件工程
- 11 篇 控制科学与工程
- 7 篇 材料科学与工程（可...
- 7 篇 土木工程
- 6 篇 动力工程及工程热...
- 5 篇 仪器科学与技术
- 3 篇 冶金工程
- 3 篇 化学工程与技术
- 3 篇 网络空间安全
- 2 篇 光学工程
- 2 篇 石油与天然气工程
- 2 篇 航空宇航科学与技...
- 1 篇 力学（可授工学、理...
- 1 篇 机械工程
- 1 篇 建筑学
- 1 篇 交通运输工程
43 篇 理学
- 21 篇 数学
- 21 篇 物理学
- 6 篇 统计学（可授理学、...
- 5 篇 化学
- 3 篇 系统科学
6 篇 管理学
- 5 篇 管理科学与工程(可...
1 篇 经济学
- 1 篇 应用经济学
1 篇 农学
1 篇 医学

主题

19 篇 operational ampl...
13 篇 computational mo...
11 篇 computer archite...
11 篇 logic gates
10 篇 adaptive filters
10 篇 field programmab...
9 篇 routing
9 篇 transistors
7 篇 task analysis
7 篇 capacitance
7 篇 handheld compute...
7 篇 jfets
7 篇 low pass filters
7 篇 hardware
7 篇 resistors
6 篇 adaptive arrays
6 篇 libraries
6 篇 capacitors
6 篇 calibration
6 篇 standards

机构

33 篇 don state techni...
20 篇 institute for de...
18 篇 institute for de...
14 篇 department of in...
13 篇 institute for de...
12 篇 institute for de...
9 篇 southern federal...
9 篇 institute for de...
7 篇 southern federal...
7 篇 institute for de...
7 篇 don state techni...
6 篇 institute for de...
6 篇 don state techni...
5 篇 institute of mic...
5 篇 department of in...
5 篇 national univers...
4 篇 department of au...
4 篇 south federal un...
4 篇 institute for de...
4 篇 institute for de...

作者

21 篇 nikolay n. proko...
16 篇 djigan victor
14 篇 prokopenko nikol...
12 篇 anna v. bugakova
10 篇 n. n. levchenko
10 篇 a. s. okunev
10 篇 victor djigan
8 篇 d. n. zmejev
8 篇 prokopenko nikol...
7 篇 denisenko darya
7 篇 sergey v. gavril...
7 篇 chumakov vladisl...
6 篇 v. i. djigan
6 篇 djigan v.i.
6 篇 darya yu. denise...
6 篇 oleg v. dvorniko...
6 篇 mariya a. zaplet...
6 篇 tchekhovski vlad...
6 篇 dvornikov oleg v...
6 篇 nikolay v. butyr...

语言

171 篇 英文
3 篇 其他
2 篇 中文

检索条件"机构=Institute for Design Problems in Microelectronics of RAS"

共 176 条记录，以下是81-90 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

I/O processor as the device for computing process management in the PDCS “Buran”

I/O processor as the device for computing process management...

引用

East-West design & Test Symposium (EWDTS)

作者： N. N. Levchenko A. S. Okunev A. L. Stempkovsky D. N. Zmejev (IPPM RAS) Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9781509006946

The paper presents the main differences of the new computing model and the system that implements this model from traditional dataflow systems. The parallel dataflow computing system architecture and I/O processor are briefly described. I/O processor is one of the main management elements of computing process in the system. Functionality of the token-generating unit and various input-output modes are also described. The data obtained with some experiments, which were carried out at the modelling programme for a number of problems, are given.

关键词： Computational modeling Context Memory management Handheld computers Algorithm design and analysis Multicore processing

来源：评论

学校读者我要写书评

暂无评论

The current state of evolution of content addressable memory architecture and aspects of its usage in the PDCS “Buran”

The current state of evolution of content addressable memory...

引用

East-West design & Test Symposium (EWDTS)

作者： E. N. Kuzmin N. N. Levchenko A. S. Okunev D. N. Zmejev Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Moscow Russia

The article provides an overview of the main directions of the development of architectures of content addressable memory and associative processors. The main problems that are facing the developers of these devices are identified. The description of the content addressable memory of keys in the matching processor, which is the main computation process control device in the parallel dataflow computing system (PDCS) “Buran”, is given. Existing methods to increase the speed and reduce power consumption for various types of content addressable memory (CAM, TCAM, etc.) are considered. Various TCAM architectures implemented on the nonvolatile memory technology, as well as associative processors are described.

关键词： Microprocessors Associative memory Program processors Power demand Random access memory Memory management

来源：评论

学校读者我要写书评

暂无评论

Solutions to Problem of CAM Overflow in the Parallel Dataflow Computing System “Buran”

Solutions to Problem of CAM Overflow in the Parallel Dataflo...

引用

East-West design & Test Symposium (EWDTS)

作者： N. N. Levchenko A. S. Okunev D.N. Zmejev IPPM RAS Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9781538657119

The article presents one of the problems solved in the design of the parallel dataflow computing system that implements the dataflow computing model with the dynamically formed context. Hardware content addressable memory of the matching processor of this system allows effective implementation of the basic principles of the dataflow computing model and should not be overflowed in the process of solving the task. The reasons that can cause an overflow of the content addressable memory of the PDCS are described, as well as the main options for solving this problem.

关键词： Task analysis Associative memory Computational modeling Hardware Handheld computers Computer architecture Context

来源：评论

学校读者我要写书评

暂无评论

Logi-thermal analysis of digital circuits using mixed-signal simulator Questa ADMS

Logi-thermal analysis of digital circuits using mixed-signal...

引用

East-West design & Test Symposium (EWDTS)

作者： K.O. Petrosyants N.I. Rjabov Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Moscow Russia

ISBN: (纸本)9781479920976

CAD sybsystem for logi-thermal analysis of the digital circuits is presented. Logical circuits are described by VHDL language. Thermal regimes are calculated by electro-thermal analogy method. For the calculation of the thermal resistances and capacitances the thermal 3D simulator Overheat-IC based on semi-analytical solution of three-dimensional heat conduction equation is used. For simultaneous calculation of logical and thermal characteristics of IC analog and mixed-signal simulator Questa ADMS is used.

关键词： Thermal resistance Integrated circuit modeling Thermal analysis Mathematical model Layout Radiation detectors Capacitance

来源：评论

学校读者我要写书评

暂无评论

Dataflow computing model — Perspectives, advantages and implementation

Dataflow computing model — Perspectives, advantages and imp...

引用

East-West design & Test Symposium (EWDTS)

作者： A. D. Ivannikov N. N. Levchenko A. S. Okunev A. L. Stempkovsky D. N. Zmejev Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Moscow Russia

The problems of parallelizing computations and increasing real performance are among the main ones for high-performance computing systems. The article describes a new dataflow computing model and architecture, which allow addressing these problems. Methods for solving other problems of classical dataflow systems and traditional cluster supercomputers by the parallel dataflow computing system are also presented. The experiment results for one of the task are shown. It is concluded that the new dataflow computing model is promising.

关键词： Computational modeling Computer architecture Hardware Handheld computers Software

来源：评论

学校读者我要写书评

暂无评论

Approaches to the development of various sets of nodes and blocks for the PDCS matching processor

Approaches to the development of various sets of nodes and b...

引用

East-West design & Test Symposium (EWDTS)

作者： N. N. Levchenko A. S. Okunev D. N. Zmejev Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Moscow Russia

This article describes approaches to building a set of nodes and blocks that are sufficient to create the matching processor for the parallel dataflow computing system. Investigations of various sets of nodes and blocks of the matching processor have been carried out. As a result, some regularities were revealed characteristic for hardware-software solutions that implement the dataflow computing model. The approaches to composing the matching processor are presented. The research data will be used to create special computers for a specific range of tasks.

关键词： Computational modeling Hardware Context Context modeling Computer architecture Handheld computers

来源：评论

学校读者我要写书评

暂无评论

The PDCS “Buran” operating efficiency improvement ways

The PDCS “Buran” operating efficiency improvement ways

引用

East-West design & Test Symposium (EWDTS)

作者： A. V. Klimov N. N. Levchenko A. S. Okunev A. L. Stempkovsky D. N. Zmejev (IPPM RAS) Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9781509006946

This paper outlines the architecture of parallel dataflow computing system and its general parameters, which could be modified to improve the operating efficiency of the system for one or another class of problems. Distribution functions allow to improve operating efficiency of the system due to scalability improvement of the task (paralleling on a greater number of computational cores). Other adaptation methods of the computing system for various tasks are given.

关键词： Computational modeling Distribution functions Handheld computers Computer architecture Adaptation models Hardware Parallel processing

来源：评论

学校读者我要写书评

暂无评论

The Modification of the ABC Synthesis Algorithm for FPGAs Considering Architecture Features

The Modification of the ABC Synthesis Algorithm for FPGAs Co...

引用

IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

作者： Ivan V. Tiunov Nikolay O. Vasilyev Chair of Comprehensive Information Security Institute for Design Problems in Microelectronics of RAS Zelenograd Russia

ISBN: (数字)9781665404761

ISBN: (纸本)9781665446426

ABC is a tool that solves the logic optimization and technology mapping tasks in the digital circuits design flow. It is suitable for both custom and FPGA design flows. This tool is a technology independent solution and, accordingly, does not take the architectural features of the target FPGA into account. Although considering these features can significantly decrease the occupied area, in terms of programmable logic blocks and interconnections. This article presents modifications of the logic synthesis algorithms used in the ABC tool. Applying these modifications allows to obtain a more appropriate description of the circuit for performing logic architecture-oriented resynthesis.

关键词： Integrated circuit interconnections Tools Logic gates Time factors Task analysis Field programmable gate arrays Optimization

来源：评论

学校读者我要写书评

暂无评论

Comparison of Complementary JFET Parameters on Technological Processes of JSC "integral" (Minsk) and JSC "sPE "pulsar" (Moscow) at Low Temperatures

Comparison of Complementary JFET Parameters on Technological...

引用

2020 Moscow Workshop on Electronic and Networking Technologies, MWENT 2020

作者： Dvornikov, Oleg V. Dziatlau, Valentin L. Tchekhovski, Vladimir A. Prokopenko, Nikolay N. Drozdov, Dmitry G. Savchenko, Eugene M. Minsk Research Instrument-Making Institute Minsk Belarus Institute for Nuclear Problems of Belarusian State University Minsk Belarus Belarusian State University Institute for Nuclear Problems Minsk Belarus Institute for Design Problems in Microelectronics of RAS Don State Technical University Rostov-on-Don Zelenograd Russia JSC Scientific and Production Enterprise Pulsar Moscow Russia Moscow Russia

ISBN: (纸本)9781728125718

The volt-Ampere characteristics (VAC) at temperatures from minus 197 ° C to 30 ° C of n-JFET and p-JFET, manufactured at JSC "SPE "Pulsar" using a complementary bipolar technological route, are considered. Features of the VACs are described and the obtained temperature approximations of the main parameters are given. We have compared the JFET's VACs manufactured at JSC "SPE "Pulsar" and JSC "Integral". © 2020 IEEE.

关键词： Junction gate field effect transistors

来源：评论

学校读者我要写书评

暂无评论

Development of an IP-cores Libraries as Part of the design Flow of Integrated Circuits on FPGA

Development of an IP-cores Libraries as Part of the Design F...

引用

IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW)

作者： Vasilii M. Khvatov Daniil A. Zheleznikov Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Moscow Russia

ISBN: (数字)9781665404761

ISBN: (纸本)9781665446426

IP-core is a block with a complex function that can be re-used in integrated circuits design. There are two types of FPGA IP-cores: hard IP-core and soft IP-core. Hard IP-cores have an exact location and pre-routed interconnects while soft IP-cores can be synthesized from logic elements and should be placed and routed. To use IP-cores in automated design flow of integrated circuits on FPGA it is necessary to develop IP-cores libraries that allow identifying blocks on every stage of *** article shows IP-core libraries types and forms used as a part of design flow developed by IPPM ras for Russian FPGA. It describes challenges of libraries for logical synthesis development and automatic mapping on an existing basis. The paper presents libraries needed by CAD on every stage of physical design for clustering, placement and routing. Also, it considers soft and hard IP-cores libraries distinct features and methods of their formation taking into account the FPGA architecture.

关键词： Integrated circuit synthesis Layout Logic gates Routing Libraries Field programmable gate arrays Physical design

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共18页 << < 5 6 7 8 9 10 11 12 13 14 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：