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2023 Antennas design and Measurement International Conference, ADMInC 2023

作者： Djigan, Victor I. Institute for Design Problems in Microelectronics of RAS Department of Integrated Circuits Design Methodology Moscow Russia

ISBN: (纸本)9798350326765

An adaptive antenna array based on the usage of the Linearly Constrained Recursive Least Squares algorithm for the weights calculation is considered in this paper. The array has a cylindrical shape. It has been demonstrated that the steering vector used in the formulation of the linear constraints has to take into consideration the radiation patterns of the array antennas. It is because the antennas are usually not omnidirectional ones and they are steered towards the different fixed directions according to their placement over the array surface. Due to the same reason the number of the interference signals, which a cylindrical adaptive antenna array is able to suppress, is much less than the number of the weights of the array. The cylindric array efficiency and the confirmation of the above-mentioned features is demonstrated by means of the simulation. © 2023 IEEE.

关键词： Directional patterns (antenna)

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Adaptive Cancellation of Engine Noise in Vehicle Cabin

Adaptive Cancellation of Engine Noise in Vehicle Cabin

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2023 Systems of Signal Synchronization, Generating and Processing in Telecommunications, SYNCHROINFO 2023

作者： Djigan, V.I. Institute for Design Problems in Microelectronics of Ras Department of Integrated Circuits Design Methodology Moscow Russia

ISBN: (纸本)9798350348316

This paper presents the adaptive noise canceller for the suppression of noise caused by a rotated engine in a vehicle cabin. The canceller uses two microphones to accept the background signals for the processing. One microphone is installed close to the vehicle engine, i.e. outside the cabin. It allows to isolate this microphone from the near-end speaker's voice which is accepted by the second microphone and is transmitted to the far-end speaker. At the same time, the engine noise penetrates to the cabin and is accepted by the second microphone. As a result, the transmitted voice signal becomes noisy. This noise has to be cancelled priory the voice signal transmitting. Because the engine noise is rather colored than white, the efficiency of usage in the noise canceller the computationally simple adaptive filters based the gradient search is low. This paper considers the usage of the computationally complex but functionally efficient Recursive Least Squares (RLS) adaptive filters in this task. Simulation demonstrates a better performance of the RLS noise canceller comparing to the gradient search based Normalized Least Mean Square (NLMS) noise canceller in the considered scenario. © 2023 IEEE.

关键词： Adaptive filters

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Multichannel Acoustic Echo Canceller Based on Fast Affine Projection Algorithm 25

Multichannel Acoustic Echo Canceller Based on Fast Affine Pr...

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25th International Conference on Digital Signal Processing and its Applications, DSPA 2023

作者： Djigan, Victor Department of Integrated Circuits Design Methodology Institute for Design Problems in Microelectronics of Ras Moscow Russia

ISBN: (纸本)9798350337235

The task of the identification of the multichannel linear system with long channel impulse responses is considered in this paper. The multichannel acoustic echo cancellation in the closed rooms is an example of this task. Dependently on the room size, its decoration and the signal sampling frequency value the duration of the identified impulse responses may take a few thousand samples. To solve this task a multichannel adaptive filter with the corresponding large number of weights is required. The implementation of such filters is a difficult task as the arithmetic complexity of the adaptive filters depends on the number of the filter weights. Due to this reason the effective time-domain Recursive Least Squares (RLS) adaptive filters even in their fast (computationally efficient) forms are rarely used in the acoustic echo cancellers. The computationally simple but less effective time-domain Least Means Squares (LMS) or the Normalized LMS (NLMS) adaptive filters are usually used for this purpose. However, such filters have a number of well-known drawbacks. The slow convergence is one of them when the correlated or nonstationary signals are processed. Speech is an example of such signals. The frequency-domain LMS/NLMS adaptive filters de-correlate the signals. These filters have a smaller computational complexity comparing to their time-domain prototypes. However, as the signals are processed using the blocks of the samples, the frequency-domain adaptive filters introduce the output signal delay and demonstrate a slower convergence because their weights are updated only once per block. This decreases the tracking ability of the frequency-domain adaptive filters. The ability is an important feature of the adaptive filters in the acoustic echo cancellation task because the acoustic medium is usually a not time-invariant one. The usage of the Fast Affine Projection (FAP) adaptive filter is the tradeoff between the acoustic echo canceller efficiency and its complexity. Su

关键词： Adaptive filters

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Features of TCAD and SPICE Simulation of a Charged Particle Impact into a 6T SRAM Cell Manufactured Using the CMOS 28-nm Technology Node

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Russian microelectronics 2024年第7期53卷 737-743页

作者： Petrosyants, K.O. Silkin, D.S. Popov, D.A. Ismail-Zade, M.R. Kharitonov, I.A. Pereverzev, L.E. Morozov, A.A. Turgenev, P.V. National Research University Higher School of Economics Moscow Russia Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia ООО AlphaCHIP Moscow Russia

Abstract—: With a decrease in the size of transistors, the conditions arise when the impact of one particle affects several transistors in the composition of a memory cell. Therefore, during simulation it is not sufficient to take into account one transistor directly hit by a particle. In this study, a full-size 3D model of two n-channel transistors that are part of a 6T memory cell in which the charged particle enters is considered. A particle impact simulation procedure is proposed that makes it possible to calculate the current pulse after the impact in a TCAD simulator and the response of memory cell circuit to an impact in a SPICE simulator using SPICE models. This procedure allows combining the advantages of the TCAD and SPICE calculations and achieve consistency between accuracy and the speed of simulation. The issues of determining the parameters of the TCAD model of a particle impact, the occurrence of a current pulse after a particle impact near a transistor in the on state, and the influence of the current of this transistor on the operation of a memory cell are considered. A technique of specifying the complex distribution profiles of charge carriers induced by particle impact in a TCAD simulator is proposed. Several cases of particle impact with different linear energy transfer (LET) values are simulated and an example of determining the critical LET value for a 6T SRAM cell with a design code of 28 nm is shown. The tailored parameters of the physical structure of the transistor make it possible to simulate the characteristics of transistors manufactured using the 28-nm CMOS technology node. © Pleiades Publishing, Ltd. 2024.

关键词： CMOS integrated circuits

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Methods for Reducing the Number of Matching Operations in the Content-Addressable Memory of the Parallel Dataflow Computing System 'Buran' 3

Methods for Reducing the Number of Matching Operations in th...

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3rd IEEE International Conference on problems of Informatics, Electronics and Radio Engineering, PIERE 2024

作者： Levchenko, Nickolay N. Zmejev, Dmitry N. Klimov, Arkadiy V. Nrc 'Kurchatov institute' Department for Design Problems in Microelectronics Moscow Russia

ISBN: (纸本)9798331516321

The paper describes the dataflow computing model and the architecture of the parallel dataflow computing system implementing it. This computing model and architecture are one of the approaches to solving the problem of increasing the real performance of computing systems. The paper describes the principles of operation of hardware content-addressable memory, which most effectively implements the principles of the dataflow computing model. One of the important problems with such memory is its high power consumption during matching operations. Methods for reducing the number of matching operations and the number of compared bits (bits involved in the matching process) are proposed. Methods for reducing the number of matching operations aim to reduce 'parasitic' comparisons of bits and keys in the token matching process. The studies conducted on the behavioral block-register model of the system and the emulator of the system confirmed the applicability of these methods to reduce the number of bits compared when executing dataflow programs. © 2024 IEEE.

关键词： content-addressable memory dataflow computing model matching operations parallel dataflow computing system parasitic matchings

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Room Frequency Response Equalization Using Modified X-Filtered Adaptive Algorithms

Room Frequency Response Equalization Using Modified X-Filter...

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2022 International Siberian Conference on Control and Communications, SIBCON 2022

作者： Djigan, Victor Institute for Design Problems in Microelectronics of RAS Moscow Russia

ISBN: (纸本)9781665476287

This article presents a technology of the acoustic frequency response equalization. It is based on the usage of the modified x-filtered adaptive algorithms in the equalizers. Comparing to the traditional x-filtered algorithms, the modified ones allow to accelerate the equalizer convergence if the computationally simple LMS or the NLMS adaptive algorithms based on the gradient search strategy are used for the equalizer weights computation. Besides, the modification allows to use the computationally complex but simultaneously efficient RLS adaptive algorithms in the x-filtered mode because the algorithms cannot be used in the traditional x-filtered mode. The proposed equalizer architectures and the computational procedures of the traditional and modified adaptive filtering algorithms are presented. Simulation demonstrates a better performance of the modified algorithms comparing to the traditional ones in the following terms: the equalized frequency response ripple value, the proximity of the PSD curves of the undistorted speech signal and the signal passed through the equalizer and acoustic medium, the initial duration of the transient response of the error signal and the response steady-state value. © 2022 IEEE.

关键词： Adaptive filters

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Improving Reliability-driven Resynthesis with Better Initial Structure

Improving Reliability-driven Resynthesis with Better Initial...

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2022 Conference of Russian Young Researchers in Electrical and Electronic Engineering, ElConRus 2022

作者： Stempkovsky, Alexander L. Telpukhov, Dmitry V. Nadolenko, Vladislav V. Institute for Design Problems in Microelectronics of Ras Moscow Russia

ISBN: (纸本)9781665409933

This paper presents a synthesis algorithm for combinational logic circuits in a given technology basis aimed at reliability optimization. Input data for the algorithm is a circuit in AIG format and a standard cell library, the output is Verilog description of the synthesized circuit. Several metrics based on logical masking probabilities are discussed providing different levels of precision for the cost of different amount of technology information ranging from none to reliability-oriented characterization results. The proposed algorithm is based on the classical tree covering algorithm adapted to optimize reliability characteristics. Signal propagation paths through inverting and non-inverting outputs of each tree are considered separately to give the algorithm more options while keeping cost function computation fast and accurate. The algorithm was tested on circuits from ISCAS'85 benchmark converted to AIGs via the ABC tool. Synthesized circuits were then given as an input to the reliability-driven resynthesis algorithm in order to further improve their fault tolerance. The final results were compared to those of the same resynthesis algorithm given ABC's covering as an input. © 2022 IEEE.

关键词： Logic Synthesis

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Simulated Annealing Based Placement in FPGAs with a Modified Permutation Operator and Congestion Optimization 3

Simulated Annealing Based Placement in FPGAs with a Modified...

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3rd IEEE International Conference on problems of Informatics, Electronics and Radio Engineering, PIERE 2024

作者： Chochaev, Rustam Zh. Zhuravlev, Vladislav A. Zheleznikov, Daniil A. Nrc 'Kurchatov institute' Dept. of design problems in microelectronics Zelenograd Moscow Russia

ISBN: (纸本)9798331516321

A placement is one of the key stages in the FPGA design flow. The quality of the resulting placement affects the routing results and, therefore, the performance of the designed circuits. In this paper we present a flat simulated annealing based placement algorithm. The key features of the developed algorithm are modified move operator, which reduces the solution search space, and congestion optimization based on the nets overlap method. The developed algorithm has been tested on an open set of circuits and compared with three placement algorithms: basic flat simulated annealing based placement algorithm, multilevel placement algorithm and flat placement algorithm without congestion estimation. The experimental results demonstrate that the developed algorithm reduces the routing time by 17% on average and the number of used routing resources by 20% on average. Moreover, the developed algorithm reduces the congestion by an average of 15% and increases the routability while increasing the total wirelength due to the reduction of the solution search space. © 2024 IEEE.

关键词： Simulated annealing

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CAD Architecture for Expansion of WSL-Based Combinational Circuits Dataset

CAD Architecture for Expansion of WSL-Based Combinational Ci...

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2024 International Russian Smart Industry Conference, SmartIndustryCon 2024

作者： Zunin, V.V. Stempkovsky, A.L. Solovyev, R.A. Hse University Moscow Russia Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9798350395044

The paper provides an overview of the current state of research in the field of combinational circuits reliability and parameters. Architecture of OpenLane flow, its components and main stages of work are described. Based on this flow, the main parameters are provided that will be used for augmentation and expansion of combinational circuits dataset and further testing. Previously developed software was elaborated to use OpenLane as its part. That is, now WSL (Ubuntu) can be used to launch OpenLane workflow from a Windows program without copying data from/to Linux system;subsequent parsing of the results to highlight the necessary parameters is implemented;parameters are saved to combinational circuits dataset. The modified software was tested for circuit generation and parameters calculation. © 2024 IEEE.

关键词： Timing circuits

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Formation of IP-Core Libraries in the User IC design Flow for FPGAs and RSoCs

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Russian microelectronics 2022年第7期51卷 567-572页

作者： Khvatov, V.M. Gavrilov, S.V. Institute for Design Problems in Microelectronics of the Russian Academy of Sciences Moscow Russia

Abstract: Complex functional blocks or intellectual property (IP) cores are developed and used to speed up the user IC design flow and improve their final characteristics. There are two IP-cores types—soft IP-cores and hard IP-cores. A hard IP core has a fixed on-chip layout and pre-routed interconnects, while a soft IP core consists of logic gates and requires placement and routing. For an automated flow for designing ICs based on FPGAs and reconfigurable systems on a chip (RSoC) it is necessary to develop core libraries that allow them to be identified at each stage of the design flow. The paper shows various types and formats of libraries of soft and hard IP-cores used in the design flow for ICs based on FPGAs and Russian-made RSoCs. Methods for designing libraries of necessary CAD systems at the stages of logical synthesis, automatic technological mapping and layout synthesis are described. The characteristic features of soft and hard IP-cores libraries, as well as methods for their formation, are considered taking into account the architecture of FPGAs and RSoCs. The proposed design methods make it possible to develop libraries that are necessary for the automated implementation of all types of IP-cores, taking into account the advantages of the architecture of basic FPGAs and RSoCs. © 2022, Pleiades Publishing, Ltd.

关键词： Field programmable gate arrays (FPGA)

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