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Dynamic system eigenvalue extraction using a linear echo state network for small-signal stability analysis - A novel application

Dynamic system eigenvalue extraction using a linear echo sta...

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2010 6th IEEE World Congress on Computational Intelligence, WCCI 2010 - 2010 International Joint Conference on Neural Networks, IJCNN 2010

作者： Liang, Jiaqi Dai, Jing Venayagamoorthy, Ganesh K. Harley, Ronald G. School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA 30332 United States University of KwaZulu-Natal Durban South Africa Real-Time Power and Intelligent Systems Laboratory Missouri University of Science and Technology Rolla MO 65409 United States

ISBN: (纸本)9781424469178

A large nonlinear dynamic system usually has complex dynamic modes corresponding to the system's eigenvalues. These eigenvalues govern the system's local behavior and thus are critical information for designing system operation and control strategies. Without the availability of the system's analytical model, which is often the case for large nonlinear systems, the system's eigenvalues need to be estimated. A linear echo state network (ESN) based method for extracting observable eigenvalues of a dynamic system together with the participation factors of these eigenvalues in the accessible system states is presented in this paper. A linear ESN is first trained to track the dynamic system's local responses under injected small perturbation signals. The dynamic system's eigenvalues are then extracted from the ESN's weight matrices. Given the merit of fast training of ESNs, the ESN can be quickly retrained once the system operating point changes, and the system eigenvalues can be reestimated. Application of the proposed eigenvalue extraction method in the power system small-signal analysis is presented to demonstrate the effectiveness of the proposed method. © 2010 IEEE.

关键词： Dynamical systems

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Efficient test suite reduction by merging pairs of suitable test cases 10

Efficient test suite reduction by merging pairs of suitable ...

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Proceedings of the 2010 international conference on Models in software engineering

作者： Harald Cichos Thomas S. Heinze Real-time Systems Lab TU Darmstadt Darmstadt Germany Institute of Computer Science Friedrich Schiller University of Jena Jena Germany

ISBN: (纸本)9783642212093

During the development and maintenance of software, the size of a test suite often increases to such an extent that the costs allocated for its execution are exceeded. In this case, the test suite needs to be reduced. A number of approaches address the problem of test suite reduction. Most of them consider the removal or merging of test cases. However, less attention has been paid to the identification of test cases that are suitable for *** this paper, we present a novel approach to fill this gap. Using this approach allows for the identification of test case pairs that, when merged, have a high potential for test suite reduction. We show that two test suites reduced by our approach are considerably smaller in size than those, whose merged test cases were selected randomly. Additionally, we examine the effect of composite test goals on the reduction ratio.

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High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulations

High-level timing analysis of concurrent applications on MPS...

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IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Roman Plyaskin Alejandro Masrur Martin Geier Samarjit Chakraborty Andreas Herkersdorf Institute of Integrated Systems Technische Universität München Munich Germany Institute of Real-Time Computer Systems Technische Universität München Munich Germany

Due to the growing complexity of multiprocessor systems-on-chip (MPSoCs), there is an increasing demand on efficient design space exploration techniques. In addition to the analysis of diverse hardware architectures, these techniques should assist the designer in the flexible evaluation of various scheduling policies and application mappings while taking effects of the shared on-chip communication infrastructure into account. Most available simulation approaches are either unable to cover all these aspects jointly or have poor simulation performance. In this paper, we present a framework for timing analysis of MPSoC architectures using abstract and yet accurate traces. The traces capture both precise processing latencies and memory access patterns and represent application- and OS-related workload. Performance estimation is performed by an interleaved execution of the traces on a highly configurable multiprocessor platform modeled in our trace-driven SystemC TLM simulator. Using the flexible scheduler model presented in this paper, various mappings and scheduling policies can be rapidly evaluated while considering on-chip interconnect contention and usage of shared resources. Due to the abstraction of the trace-driven simulations, the proposed framework allows for both fast and accurate explorations of MPSoC design alternatives.

关键词： computer architecture Context Synchronization System-on-a-chip Scheduling Computational modeling

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Efficient Reduction of Model-Based Generated Test Suites through Test Case Pair Prioritization

Efficient Reduction of Model-Based Generated Test Suites thr...

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Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa)

作者： Harald Cichos Thomas S. Heinze Real-Time Systems Laboratory Technische Universität Darmstadt Darmstadt Germany Institute of Computer Science Friedrich-Schiller-Universitat Jena Jena Germany

During the development and maintenance of software, test suites often reach a size that exceeds the costs allocated for test suite execution. In such a case, the test suite needs to be reduced. Many papers are dedicated to the problem of test suite reduction. Most of them consider the removal or merging of test cases. However, less attention has been paid to the identification of test case pairs, which are eminently suitable for merging. In this paper, we fill this gap by presenting a novel approach that helps identifying those test case pairs within a given set of systematically generated test cases which, when merged, have potential for high test suite reduction. As a result, test suites reduced by our approach are considerably smaller in size than those, whose pairs are selected randomly.

关键词： Merging Fault detection Unified modeling language Testing Iron Barium computer aided software engineering

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Switched FlexRay: Increasing the effective bandwidth and safety of FlexRay networks

Switched FlexRay: Increasing the effective bandwidth and saf...

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International Conference on Emerging Technologies and Factory Automation (ETFA)

作者： Paul Milbredt Bart Vermeulen Gökhan Tabanoglu Martin Lukasiewycz AUDI AG Germany Central Research and Development AAL DiSA NXP Semiconductors Netherlands Volkswagen AG Germany Institute for Real Time Computer Systems Technical University Munich Germany

With the continued demand for more and innovative functions in series automobiles, significantly higher data-rates and more reliable communication are necessary than traditional automotive bus systems, e.g., the controller area network (CAN), provide. In this paper, we present a novel hardware device for FlexRay networks, which splits the bus into separate branches and operates as a selective central switch. The proposed device is capable of increasing both the available bandwidth and safety of existing FlexRay networks. The bandwidth is increased by enabling the scheduling of multiple messages in parallel on disjoint sets of branches. The device can furthermore serve as a central bus guardian (CBG), protecting the majority of the participants on the network from so-called babbling idiots and short circuits, by isolating a faulty component on its respective branch. The proposed device is fully compatible with the existing FlexRay specifications and transparently extends a system, requiring no modifications to the existing FlexRay bus participants. The architectural challenges of a FlexRay switch/CBG, its subsequent proof-of-concept implementation on an FPGA-platform, and our experimental results are described in detail.

关键词： Switches Synchronization Topology Ethernet networks Schedules Bandwidth Network topology

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Effects of variable solar irradiance on the reactive power compensation for large solar farm

Effects of variable solar irradiance on the reactive power c...

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iREP Symposium on Bulk Power System Dynamics and Control

作者： Dustin F. Howard Ronald G. Harley Jiaqi Liang Ganesh K. Venayagamoorthy School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA Real-Time Power and Intelligent Systems Laboratory Missouri University of Science and Technology Rolla MO USA

Dish-Stirling systems are a form of concentrating solar power (CSP) emerging as an efficient and reliable source of renewable energy. Various technical hurdles are involved in the grid interconnection of dish-Stirling systems, particularly with issues related to power factor correction, low voltage ride-through capability, and reactive power planning. While there are no grid-interconnection requirements specific to dish-Stirling technology, the requirements currently established for wind farms are used as a starting point due to the similar design and operating characteristics between wind farms and dish-Stirling solar farms. A dish-Stirling solar farm requires external reactive power compensation to meet the power factor requirements presently set for wind farms. The following paper provides a brief overview of dish-Stirling technology, along with an analysis of methods for meeting power factor grid interconnection requirements and maintaining necessary voltage levels under varying irradiance conditions due to cloud cover. Simulation results for voltage and power factor of the solar farm are provided for both steady state and cloud transient conditions within a 12-bus network.

关键词： Reactive power Stirling engines Generators Induction machines Space heating

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Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach

Evaluating the impact of communication latency on applicatio...

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IEEE International Conference on Industrial Informatics (INDIN)

作者： Leandro Soares Indrusiak Luciano Copello Ost Fernando Gehm Moraes Sanna Määttä Jari Nurmi Leandro Möller Manfred Glesner Real-Time Systems Group-Computer Science Department University of York UK Informatics Department Catholic University of Rio Grande do Sul Porto Alegre Brazil Department of Computer Systems Tampere University of Technology Finland Institute of Microelectronic Systems Darmstadt University of Technology Germany

ISBN: (纸本)9781424472987;9781424473007

The evaluation of communication latency in multiprocessor platforms requires the profiling of the application, the description of the architecture of the platform and of the mapping of application tasks onto processing cores. In this paper, we describe a layered approach that allows application developers to obtain accurate figures for communication latency from an abstract model of the application functionality. A complete separation of concerns is a critical part of this approach, so the major contribution here is the definition of interfaces between different layers: an abstract application model, its executable counterpart, the mapping heuristic and the multiprocessor platform model. Case studies with a realistic application and a NoC-based multiprocessor platform show the potential of the proposed approach using two different system evaluation techniques: simulation and static analysis.

关键词： Delay Unified modeling language Application software real time systems Network-on-a-chip System-on-a-chip computer science Informatics Microelectronics Analytical models

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Dynamic system eigenvalue extraction using a linear echo state network for small-signal stability analysis - a novel application

Dynamic system eigenvalue extraction using a linear echo sta...

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International Joint Conference on Neural Networks (IJCNN)

作者： Jiaqi Liang Jing Dai Ganesh K. Venayagamoorthy Ronald G. Harley Honorary Research Associate University of KwaZulu-Natal Durban South Africa School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA Real Time Power and Intelligent Systems Laboratory Missouri University of Science and Technology Rolla MO USA

关键词： Eigenvalues and eigenfunctions Power system dynamics Nonlinear dynamical systems Training Generators

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Fast model-based test case classification for performance analysis of multimedia MPSoC platforms 09

Fast model-based test case classification for performance an...

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Embedded systems Week 2009, ESWEEK 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009

作者： Gangadharan, Deepak Chakraborty, Samarjit Zimmermann, Roger Department of Computer Science National University of Singapore Singapore Institute for Real-Time Computer Systems TU Munich Germany

ISBN: (纸本)9781605586281

Currently, performance analysis of multimedia-MPSoC platforms largely rely on simulation. The execution of one or more applications on such a platform is simulated for a library of test video clips. If all specified performance constraints are satisfied for this library, then the architecture is assumed to be well-designed. This is similar to testing software for functional correctness. However, in contrast to functional testing, simulating a set of video clips for a complex application/architecture is extremely time consuming. In this paper we propose a technique for clustering a library of video clips, such that it is sufficient to simulate only one clip from each cluster rather than the entire library. Our clustering is scalable, i.e., the number of clusters may be determined based on the number of clips that the system designer wishes to simulate (which is independent of the input library size). For each video clip in the library, we perform a fast bitstream analysis from which the workload generated while processing this clip on the given architecture may be estimated. This workload information, in conjunction with a workload model and a performance model of the architecture, is used for the clustering. This entire process does not involve any simulation and is hence extremely fast. We illustrate its utility through a detailed case study using an MPEG-2 decoder application running on an MPSoC platform. As part of validation of our methodology, it was observed that video clips falling into the same cluster exhibit similar worst case buffer backlogs and worst case delays for one macroblock. Overall the results demonstrate that the proposed method provides a very fast and accurate analysis and hence can be of significant benefit to the system designer. Copyright 2009 ACM.

关键词： Software testing

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Evaluating design trade-offs in customizable processors 09

Evaluating design trade-offs in customizable processors

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2009 46th ACM/IEEE Design Automation Conference, DAC 2009

作者： Bordoloi, Unmesh D. Huynh, Phung Huynh Chakraborty, Samarjit Mitra, Tulika Verimag Labs. France Department of Computer Science National University of Singapore Singapore Institute for Real-Time Computer Systems TU Munich Germany

ISBN: (纸本)9781605584973

The short time-to-market window for embedded systems demands automation of design methodologies for customizable processors. Recent research advances in this direction have mostly focused on single criteria optimization, e.g., optimizing performance though custom instructions under pre-defined area constraint. From the designer's perspective, however, it would be more interesting if the conflicting trade-offs among multiple objectives (e.g., performance versus area) are exposed enabling an informed decision making. Unfortunately, identifying the optimal trade-off points turns out to be computationally intractable. In this paper, we present a polynomial-time approximation algorithm to systematically evaluate the design trade-offs. In particular, we explore performance-area trade-offs in the context of multi-tasking real-time embedded applications to be implemented on a customizable processor. Copyright 2009 ACM.

关键词： Embedded systems

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