This paper studies the performance and working aspects of SMT solvers on processing formulas acquired during path-sensitive static analysis and dynamic symbolic execution. We review some general patterns of building S...
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This paper studies the performance and working aspects of SMT solvers on processing formulas acquired during path-sensitive static analysis and dynamic symbolic execution. We review some general patterns of building SMT formulas in the QF_BV logic during analysis and related technical specifics. We also provide the results of comparing different solvers on two sets of requests obtained by Svace static analyzer and Anxiety dynamic symbolic execution tool. It turns out that Yices2 solver performs the best, although, for Svace, notable part of requests can be done better by other solvers. In return, Yices2 misses some features crucial to top-tier analyzers such as deterministic time limit. A brief attempt at making machine learning based solver portfolio shows that solving time can be enhanced, but requires some serious work on feature selection, while technical difficulties may render it unpractical. For Anxiety we found out that with Yices2 incremental solving is almost always faster (sometimes dozens of times faster) than non-incremental. Moreover, the more queries we solve incrementally, the higher acceleration we get.
Most Named Entity Recognition (NER) models operate under the assumption that training datasets are fully labelled. While it is valid for established datasets like CoNLL 2003 and OntoNotes, sometimes it is not feasible...
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Most Named Entity Recognition (NER) models operate under the assumption that training datasets are fully labelled. While it is valid for established datasets like CoNLL 2003 and OntoNotes, sometimes it is not feasible to obtain the complete dataset annotation. These situations may occur, for instance, after selective annotation of entities for cost reduction. This work presents an approach to finetuning BERT on such partially labelled datasets using self-supervision and label preprocessing. Our approach outperforms the previous LSTM-based label preprocessing baseline, significantly improving the performance on poorly labelled datasets. We demonstrate that following our approach while finetuning RoBERTa on CoNLL 2003 dataset with only 10% of total entities labelled is enough to reach the performance of the baseline trained on the same dataset with 50% of the entities labelled.
Graph neural networks (GNNs) have shown great promise in a variety of tasks involving graph data, including recommendation systems. However, as GNNs become more widely adopted in practical applications, concerns have ...
Automatic generation and simulation of test programs is known to be the main means for verifying microprocessors. The problem is that test program generators for new designs are often developed from scratch with littl...
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Automatic generation and simulation of test programs is known to be the main means for verifying microprocessors. The problem is that test program generators for new designs are often developed from scratch with little reuse of well-tried components. State-of-the-art tools, like Genesys-Pro and RAVEN, meet the challenge by using a model-based approach, where a microprocessor model is separated from a platform-independent generation core. However, there is still a problem. Developing a microprocessor model is rather difficult and usually requires deep knowledge of the inner-core structure and interfaces. In this paper, we describe a concept of a reconfigurable test program generator being customized with the help of architecture specifications and configuration files, which describe parameters of the microprocessor subsystems (pipeline, memory, and others). The suggested approach eases the model development and makes it possible to apply the model-based testing in the early design stages when the microprocessor architecture is frequently modified.
In this paper, a tool for automatically generating test programs for ARM VMSAv8-64 memory management units is described. The solution is based on the MicroTESK framework being developed at ISP RAS. The tool consists o...
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ISBN:
(纸本)9781509008865
In this paper, a tool for automatically generating test programs for ARM VMSAv8-64 memory management units is described. The solution is based on the MicroTESK framework being developed at ISP RAS. The tool consists of two parts: an architecture-independent test program generation core and VMSAv8-64 specifications. Such separation is not a new principle in the area -- it is applied in a number of industrial test program generators, including IBM's Genesys-Pro. The main distinction is in how specifications are represented, what sort of information is extracted from them, and how that information is exploited. In the suggested approach, specifications comprise descriptions of the memory access instructions, loads and stores, and definition of the memory management mechanisms such as translation lookaside buffers, page tables, and cache units. The tool analyzes the specifications and extracts the execution paths and inter-path dependencies. The extracted information is used to systematically enumerate test programs for a given user-defined template. Test data for a particular program are generated by using symbolic execution and constraint solving techniques.
The paper describes a method for keyterm extraction from messages of microblogs. The described approach utilizes the information obtained by the analysis of structure and content of Wikipedia. The algorithm is based o...
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The paper describes a method for keyterm extraction from messages of microblogs. The described approach utilizes the information obtained by the analysis of structure and content of Wikipedia. The algorithm is based on computation of “keyphraseness” measure for each term, i.e. an estimation of probability that it can be selected as a key in the text. The experimental study of the proposed technique demonstrated satisfactory results which significantly outpaces analogues. As a demonstration of possible application of the algorithm, the prototype of context-sensitive advertising system has been implemented. This system is able to obtain the descriptions of the goods relevant to the found keyterms from Amazon online store. Several suggestions are also made on how to utilize the information obtained by the analysis of Twitter messages in different auxiliary services.
In paper shortly describes handling calculable complex "Dnepr-2, which including a calculable machine "Dnepr-21" and handling machine "Dnepr-22" for the management by Technologies Processes (T...
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In paper shortly describes handling calculable complex "Dnepr-2, which including a calculable machine "Dnepr-21" and handling machine "Dnepr-22" for the management by Technologies Processes (TP) objects to Automatisation systems. Complex"Dnepr-2" was elaborated in institute of cybernetics AN Ukraine and his special designer bureau of mathematical machines and systems under the direction of the academician V.M. Gluchkov (Decision of CM USSR No 1250 from 12.12.1965). This complex was one of pioneer works in USSR. In him on period of 60 years of past century new and original scientific and technical decisions are realized. In complex "Dnepr-2" was realized management by the calculation and treatment in real time by objects, system of breaking, operation system with the division of time, translators from the new languages (Auto cod, Algol-60, COBOL and others).
We present the basis of the original autonomous adaptive control (AAC) methodology. It is an approach to the design of intelligent systems that simulate structure and functions of the nervous system and brain. The AAC...
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We present the basis of the original autonomous adaptive control (AAC) methodology. It is an approach to the design of intelligent systems that simulate structure and functions of the nervous system and brain. The AAC methodology idea is that structure and functions of the nervous system are forced to follow the control system conditions at an initial moment. The initial conditions are: (a) the control system (CS) is a discrete device; (b) the CS is located inside of the controlled object; (c) the CS has minimum initial knowledge. We briefly described the AAC CS structure and functions. The AAC CS can be made, for example, in neural networks form.
In this paper we describe a method for simulation-based verification of microprocessor units based on cycle-accurate contract specifications. Such specifications describe behavior of a unit in the form of precondition...
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In this paper we describe a method for simulation-based verification of microprocessor units based on cycle-accurate contract specifications. Such specifications describe behavior of a unit in the form of preconditions and postconditions of microoperations. Test sequence generation is based on traversal of FSM constructed automatically from specifications and test coverage definition. We have successfully applied the method to several units of the industrial MIPS64-compatible microprocessor.
This paper describes a new approach to visualization of scenarios within the use case-based engineering of functional requirements-the so-called video camera metaphor. The video camera metaphor facilitates involvement...
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ISBN:
(纸本)9780769507101
This paper describes a new approach to visualization of scenarios within the use case-based engineering of functional requirements-the so-called video camera metaphor. The video camera metaphor facilitates involvement of business people, customers, problem domain experts and other non-technical stakeholders into capturing and validating formal requirements models. The key tool, supporting the video camera metaphor is the so-called interface editor which allows to draft the prototype user interface and automatically generates a user-friendly front-end to the set of formal modelling tools. The essence of the video camera interface is to associate sequences of events on a UML sequence diagram or an ITU-T message sequence chart with sequences of activations of the elements of the generated user interface. The video camera interface allows capturing scenarios through direct activation of both the input and the output elements of the generated user interface. The generated user interface is also used to replay scenarios for validation purposes.
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