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Time and energy efficient service discovery in Bluetooth

Time and energy efficient service discovery in Bluetooth

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IEEE Conference on Vehicular Technology (VTC)

作者： I. Sedov S. Preuss C. Cap M. Haase D. Timmermann Department of Computer Science University of Rostock Germany Department of Computer Science Chair for Information and Communication Services University of Rostock Germany Department of Electrical Engineering and Information Technology Institute of Applied Microelectronics and Computer Science Germany

Key challenges in wireless mobile ad hoc networks are computational resource constraints, power limitations, and efficient service discovery techniques. The short range radio network technology Bluetooth suffers from long service discovery delays and high power consumption due to necessary connection establishment between discovering and discovered entity. For improving the efficiency of service discovery in Bluetooth networks we propose two new approaches. By leveraging the implicit broadcast capability of the Bluetooth inquiry procedure, we significantly reduce the service discovery time and hence lower the power consumption. Moreover, we enable the integration of resource limited devices which are incapable of taking part in service discovery themselves. Based on a performance evaluation and a comparison with legacy Bluetooth service discovery protocol (SDP), we present the benefits of our new approaches.

关键词： Energy efficiency Bluetooth Energy consumption Protocols Broadcasting Petroleum computer science Mobile ad hoc networks Personal area networks Temperature sensors

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Optimal sampling functions in nonuniform sampling driver designs to overcome the Nyquist limit

Optimal sampling functions in nonuniform sampling driver des...

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： F. Papenfuss Y. Artyukh E. Boole D. Timmermann Institute of Applied Microelectronics and Computer Science University of Rostock Germany Latvian University Riga Latvia Institute of Electronics and Computer Science (IECS) Riga Latvia

In some applications the observed samples are inherently nonuniform. In contrast to that in this paper we take advantage of deliberate nonuniform sampling and perform DSP where the classical approaches leave off. For instance think about mobile communication or digital radio. Deliberate nonuniform sampling promises increased equivalent sampling rates with reduced overall hardware costs. The equivalent sampling rate is the sampling rate that a uniform sampling device would require in order to achieve the same processing bandwidth. While the equivalent bandwidth of a realizable system may well extend into the GHz range its mean sampling rate is usually in the MHz range. Current existing prototype systems achieve 40 times the bandwidth of a classic DSP system that would operate uniformly (Artyukh et al. (1997)). Throughout the literature on nonuniform sampling (e.g. Bilinskis et al. (1992), Marvasti (2001), and Wojtiuk (2000)) many sampling schemes have been investigated. In this paper the authors discuss a nonuniform sampling scheme that is especially suited to be implemented in digital devices, thus, fully exploiting state-of-the-art ADC without violating their specifications. An analysis of the statistical properties of the algorithm is given to demonstrate common pitfalls and to prove its correctness.

关键词： Sampling methods Nonuniform sampling Bandwidth Digital signal processing Mobile communication Digital communication Hardware Costs Prototypes Algorithm design and analysis

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Optimal sampling functions in nonuniform sampling driver designs to overcome the Nyquist limit

Optimal sampling functions in nonuniform sampling driver des...

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IEEE International Conference on Multimedia and Expo (ICME)

作者： F. Papanfub Y. Artyukh E. Boole D. Timmermann Inst. of Appl. Microelectronics & Comput. Sci. Rostock Univ. Germany Institute of Electronics and Computer Science (IECS) Riga Latvia Institute of Applied Microelectronics and Computer Science University of Rostock Germany

In some applications the observed samples are inherently nonuniform. In contrast to that in this paper we take advantage of deliberate nonuniform sampling and perform DSP where the classical approaches leave off. For instance think about mobile communication or digital radio. Deliberate nonuniform sampling promises increased equivalent sampling rates with reduced overall hardware costs. The equivalent sampling rate is the sampling rate that a uniform sampling device would require in order to achieve the same processing bandwidth. While the equivalent bandwidth of a realizable system may well extend into the GHz range its mean sampling rate is usually in the MHz range. Current existing prototype systems achieve 40 times the bandwidth of a classic DSP system that would operate uniformly (cf. [Y. Artyukh, et al., Evaluation of Pseudorandom Sampling Process, 1997] and [Y. Artyukh, et al., virtual Oscilloscope of the DASP-Lab System 1997]). Throughout the literature on nonuniform sampling (e. g. [I. Bilinskis and A. Mikelsons, 1992], [F. Marvasti, 2001] and [J.J. Wojtiuk, 2000]) many sampling schemes have been investigated. In this paper the authors discuss a nonuniform sampling scheme that is especially suited to be implemented in digital devices, thus, fully exploiting state-of-the-art ADCs without violating their specifications. An analysis of the statistical properties of the algorithm is given to demonstrate common pitfalls and to prove its correctness.

关键词： Sampling methods Nonuniform sampling Bandwidth Digital signal processing Mobile communication Digital communication Hardware Costs Prototypes Oscilloscopes

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Nonuniform sampling driver design for optimal ADC utilization

Nonuniform sampling driver design for optimal ADC utilizatio...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： F. Papenfuss Y. Artyukh E. Boole D. Timmermann Inst. of Appl. Microelectron. & Comput. Sci. Rostock Univ. Germany Latvian University Riga Latvia Institute of Electronics and Computer Science (IECS) Riga Latvia Inst. of Applied Microelectronics and Computer Science University of Rostock Germany

Deliberate nonuniform sampling promises increased equivalent sampling rates with reduced overall hardware costs of the DSP system. The equivalent sampling rate is the sampling rate that a uniform sampling device would require in order to achieve the same processing bandwidth. Equivalent bandwidths of realizable systems may well extend into the GHz range while the mean sampling rate stays in the MHz range. Current prototype systems (IECS) have an equivalent bandwidth of 1.6 GHz at a mean sampling rate of 80 MHz, achieving 40 times the bandwidth of a classic DSP system that would operate uniformly at 80 MHz. Throughout the literature on nonuniform sampling, different sampling schemes have been investigated. This paper focuses on nonuniform sampling schemes optimized for fast and efficient hardware implementation. To our knowledge, this is the first proposal of an efficient nonuniform sampling driver (SD) design in the open literature.

关键词： Nonuniform sampling Sampling methods Signal sampling Bandwidth Clocks Hardware Random number generation Frequency Driver circuits computer science

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Low energy adaptive clustering hierarchy with deterministic cluster-head selection

Low energy adaptive clustering hierarchy with deterministic ...

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International Workshop on Mobile and Wireless Communications Network (MWCN)

作者： M.J. Handy M. Haase D. Timmermann Institute of Applied Microelectronics and Computer Science University of Rostock Rostock Germany

This paper focuses on reducing the power consumption of wireless microsensor networks. Therefore, a communication protocol named LEACH (low-energy adaptive clustering hierarchy) is modified. We extend LEACH's stochastic cluster-head selection algorithm by a deterministic component. Depending on the network configuration an increase of network lifetime by about 30% can be accomplished. Furthermore, we present a new approach to define lifetime of microsensor networks using three new metrics FND (First Node Dies), HNA (Half of the Nodes Alive), and LND (Last Node Dies).

关键词： Microsensors Base stations Clustering algorithms Wireless sensor networks Stochastic processes Ubiquitous computing Hardware Wireless application protocol Energy consumption Steady-state

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Framework for validation, test and analysis of real-time scheduling algorithms and scheduler implementations

Framework for validation, test and analysis of real-time sch...

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International Workshop on Rapid System Prototyping (RSP)

作者： F. Golatowski J. Hildebrandt J. Blumenthal D. Timmermann Institute of Applied Microelectronics and Computer Science University of Rostock Rostock Germany

This paper describes our work towards a rapid prototyping system for hard real-time systems focusing on scheduling algorithms and scheduler implementations. The framework aims at speeding up the decision making process during selection of a suitable scheduling algorithm for a real-time application. The framework supports various kinds of real-time scheduling algorithms, which can be simulated for evaluation purposes. Furthermore, implementations of these algorithms can be tested in a real-time operating system (RTOS) with real or synthetic workloads. The algorithms are implemented as software routines, which are part of the operating system (OS), or realized within a coprocessor to free the operating system kernel from time consuming scheduling operations. Both kinds of implementations have to provide an application programming interface that hides the algorithm from implementation issues. The target operating system of our framework is mainly RT-Linux, even though development for those systems is possible under Linux as well as Windows-NT. The framework proposed in this paper is new in that it supports the selection of the right algorithm and the right implementation for the target platform based on real-time scheduling analysis.

关键词： Algorithm design and analysis Scheduling algorithm Operating systems Real time systems Application software Prototypes Decision making System testing Software algorithms Coprocessors

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Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs

Dynamic single phase logic with self-timed stages for power ...

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2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001

作者： Grassert, F. Timmermann, D. Institute for Applied Microelectronics and Computer Science Department of Electrical Engineering and Information Technology University of Rostock Rxhard-Wagner-Str. 3 1 D-18119 Rostock Germany

ISBN: (纸本)0780366859

True single phase clock logic techniques, e.g. with alternating arranged Nand P-logic cells, yield easily to design circuits with standard cells and high speed potential. The disadvantages are a difficult clock tree design and high power consumption. To realize every logic function, dual rail or differential styles are chosen which increase clock load. This paper presents a method to speed up dynamic single clock circuits. The advantage of asynchronous logic is that the critical path delay is the sum of only the evaluation times of the single logic blocks without wasting time for waiting, latches, or redundant logic. Therefore, this work assembles small asynchronous chains of dynamic logic blocks into one period of the global clock to minimize the unused time per clock cycle (AC-TSPC). However, the synchronous single phase clocking scheme is maintained. The advantages of this method are shorter latencies for calculations, power reduction by smaller clock trees and no need for latches, and a simpler clock distribution network due to increased clock skew tolerance. The results of the simulations of an 8/spl times/8 bit multiplier in TSPC and in AC-TSPC show an enhancement in power-reduction of 40% for the logic and of 89% for the clock tree with a latency reduction of 40% and more in comparison with TSPC. © 2001 IEEE.

关键词： Forestry

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An FPGA based scheduling coprocessor for dynamic priority scheduling in hard real-time systems 10th

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10th International Conference on Field-Programmable Logic and Applications, FPL 2000

作者： Hildebrandt, Jens Timmermann, Dirk University of Rostock Institute of Applied Microelectronics and Computer Science Richard-Wagner-Str.31 D-18119 Germany

ISBN: (纸本)3540678999

In this paper we present a scheduling coprocessor device for uniprocessor computer systems running a real-time operating system (RTOS). The coprocessor shortens the scheduling time of the operating system by performing dynamic priority computation for all tasks in parallel and making a task selection according to these priorities at a higher speed than a software solution would do. This paper starts with a survey of related work and gives a motivation for the development of the proposed coprocessor architecture. We describe the architecture of our deterministic scheduling coprocessor and an efficient FPGA implementation and give a performance evaluation. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Scheduling

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Scheduling coprocessor for enhanced least-laxity-first scheduling in hard real-time systems

Scheduling coprocessor for enhanced least-laxity-first sched...

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Euromicro Conference on Real-Time Systems

作者： J. Hildebrandt F. Golatowski D. Timmermann Department of Electrical Engineering and Information Technology Institute of Applied Microelectronics and Computer Science University of Rostock Rostock Germany

Scheduling time impact on system performance increases especially when using dynamic priority algorithms, because of the enlarged computational effort at runtime. This overhead can be reduced by using dedicated hardware that does the time consuming computations necessary for scheduling. This can be a coprocessor capable of implementing dynamic scheduling algorithms which are, until now, rarely used because of their complex computations at schedule time. One of these algorithms is Least-Laxity-First (LLF). This is an optimal scheduling methodology that allows detection of time constraint violations ahead of reaching a task's deadline, but has the disadvantage of showing poor runtime behavior in some special situations ("thrashing"). In this paper, we present a universal deterministic scheduling coprocessor that implements the newly developed Enhanced Least-Laxity-First-algorithm (ELLF) which eliminates this disadvantage of LLF. Computation time of this device is rather a matter of time resolution than of the number of tasks.

关键词： Coprocessors Optimal scheduling Processor scheduling Dynamic scheduling Heuristic algorithms Scheduling algorithm Runtime System performance Hardware Time factors

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FPGA based architecture evaluation of cryptographic coprocessors for smartcards

FPGA based architecture evaluation of cryptographic coproces...

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IEEE Symposium on FPGAs for Custom Computing Machines

作者： H. Ploog D. Timmermann Institute of Applied Microelectronics and Computer Science University of Rostock Rostock Germany

In 1996, about 600 million IC cards were manufactured worldwide. Due to very small die sizes (max. 25 mm/sup 2/) smartcards encounter more severe restrictions than conventional coprocessors. We study coprocessor architectures for very fast but area efficient modular exponentiation (FME) based on Montgomery multiplication. For assessment purposes we developed an evaluation board containing a 8051 microprocessor, a XILINX FPGA and RAM with variable bus width (8b to 32b). We evaluated these architectures in terms of the main design parameters to ease design decisions for smartcards in arbitrary technologies.

关键词： Field programmable gate arrays Cryptography Coprocessors Arithmetic Clocks Manufacturing Microprocessors Power system security Read-write memory Writing

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