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Hands-free sheet music [Resources-hands on]

IEEE Spectrum 2014年第10期51卷 27-28页

作者： Gibbs, W. Institute of Electronic Computer-Aided Design Key Laboratory of High-Speed Circuit Design and Electromagnetic Compatibility Ministry of Education Xi'an China

As an old-school writer, I prefer my reading matter printed and bound. But as an avid piano player, I am sick to death of music books. The music stand on our Baldwin grand piano holds a few pages laid side by side just fine. But most piano music is sold in songbooks: double-sided pages bound to inflexible spines. These books close up on you midsong when they are new;they fall to pieces when they get old. And playing complex music without interruptions is virtually impossible unless you have an assistant to turn pages for you. · Tinkerers since the early 1900s have patented myriad mechanical page turners to address this problem, but to this day they are generally considered a pain to load, noisy, and unreliable. · After years of growling at my misbehaving music, I finally resolved to create my own solution. I set the bar high. The system should work with all of my music books, allow annotations, and turn pages while my hands remain securely on the keys. It must be big enough to show two pages of notation sharply at full size, yet compact enough to fit on my piano¿s music stand. I wanted something self-contained that would work with a digital keyboard when I play with a band. And I didn¿t want to spend more than a few hundred bucks. · Clearly, the key was ditching print in favor of pixels. I lugged my boxes of books down to a copy center, and for US $30 they ran them through a guillotine to slice off the bindings. I then used a Fujitsu ScanSnap document scanner (modified to accept large pages) to convert the books into PDFs. Calibre, an open-source e-book library organizer, let me tag and sort scores by genre, difficulty, composer, and so on. © 2014 IEEE.

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Flexible high-performance PPC on-board computer archticture based QN silicon-on-insulator technology

Flexible high-performance PPC on-board computer archticture ...

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58th International Astronautical Congress 2007

作者： Ivars, S. Glauert, W. Frickel, J. Ortner, J. Kandler, B. Zaman, J. Mueller, H. Graf, H.R. Fleischmann, F. Pfingst, U. Schiffner, M. Walter, U. Technical University of Munich Institute of Astronautics University of Erlangen-Nuremberg Department of Computer-Aided Circuit Design University of Applied Sciences Hof BayernSAT Group Diehl BGT Defence Röthenbach Germany OES GmbH

ISBN: (纸本)9781605601502

This paper gives an overview of ERViS computer, a new space computer system for extreme performance and high reliability computations. The system is based on Commercial-Of-The-Shelf (COTS) microcircuits to allow easy adaption with future state of the art CPUs. It consists of three Silicon-on-Insulator (SOI) based PowerPC750 CPUs which can either be used in parallel mode to scale performance or in triple-redundant mode to increase fault-tolerance. With its flexible operation modes and its standard I/O connectivity the system is suited for a wide range of different space missions. The conceptual ideas leading to the actual computer architecture are described and application examples are stated. Finally the status of the ERViS development is summarized. Copyright IAF/IAA. All rights reserved.

关键词： Program processors

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Formal description of test specification and ATE architecture for mixed-signal test

Formal description of test specification and ATE architectur...

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IEEE International Test Conference

作者： B. Deng W. Glauert Institute for Computer Aided Circuit Design University of Erlangen Nuremberg Erlangen Germany

This work proposes an approach to the formal description of test specifications and automatic test equipment (ATE) architectures for mixed-signal test. For this purpose, two sets of standard components are defined. A test specification and an ATE can then be described using these components and their properties. In the end, they can be represented by several mathematical matrices. Such a description, because of its clarity, is suitable for analysis using mathematical methods and, therefore, forms a basis for the automatic generation of an optimal test concept, which is now a particularly weak spot for the test program and device interface board development.

关键词： circuit testing Automatic testing Integrated circuit testing Debugging computer architecture Costs Time to market Hardware circuit synthesis Automatic test equipment

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On a high-speed Reed-Solomon Codec architecture for 43 Gb/s optical transmission systems

On a high-speed Reed-Solomon Codec architecture for 43 Gb/s ...

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International Conference on Microelectronics, MIEL

作者： T. Buerner R. Dohmen A. Zottmann M. Saeger A.J. van Wijngaarden Institute for Computer Aided Circuit Design University of Erlangen Erlangen Germany Marquardt Rietheim Germany Lucent Technologies Inc. Nuremberg Germany Lucent Teclinologirs Bell Laboratories Murray Hill NJ USA

Modern high-speed optical transmission systems rely heavily on forward error control (FEC) codes to provide quasi error-free transmission over optical channels. The ITU recommendations G.709 and G.975 that underly current optical systems prescribe the use of an FEC code of length 32640 that consists of 16 interleaved 8-error correcting [255,239] Reed-Solomon (RS) codes with 8-bit symbols. The objective is to replace this standard FEC code by a powerful RS code. An obvious candidate is a single 85-error correcting [2720,2550] RS code of length 32 640 with 12-bit symbols, that is shown to have superior random and burst error correction capabilities and to achieve a 2 dB gain relative to the standard FEC code. To implement such a code, a general high-speed parallelized and pipelined encoder and decoder (codec) architecture is developed. It is then shown that the [2720,2550] RS encoder and decoder can be realized in 0.18 /spl mu/m CMOS technology at 1.8 V for a 43 Gb/s optical transmission system with 475 k gates and 1.6 M gates, respectively. The proposed [2720,2550] RS code thus proves to be a good candidate to replace the standard FEC code.

关键词： Reed-Solomon codes Codecs High speed optical techniques Forward error correction Code standards Error correction codes Decoding CMOS technology Error correction Gain

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Implementation of a successive erasure BCH*(16,7,6) decoder and performance simulation by rapid prototyping

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Lecture Notes in computer Science

作者： Buerner, Thomas Institute for Computer Aided Circuit Design University of Erlangen Paul-Gordan-Str. 5 91052 Erlangen Germany

ISBN: (纸本)3540441085

A major problem in simulating communication systems is that, below a certain error rate, software simulation is too slow. Also software often does not allow to simulate the real system but only a somehow simplified version. Rapid prototyping can help to execute a hardware emulation of the system that is fast and represents the real behaviour too. As an example this paper describes the software simulation and hardware emulation of an extended BCH(16,7) code over an additive white Gaussian noise(AWGN) channel using binary phase shift keying (BPSK). Successive erasure decoding(SED) shows an additional gain of about 1 dB at a bit error rate of 10-6 and below, compared to a standard Berlekamp-Massey algorithm(BMA). The first two sections present the theoretical coding background, section three deals with implementation issues and section four discusses simulation and emulation results. © Springer-Verlag Berlin Heidelberg 2002.

关键词： Bit error rate

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Integration of formal specification into the standard ASIC design flow

Integration of formal specification into the standard ASIC d...

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IEEE International Symposim on High Assurance Systems Engineering

作者： W. Haas S. Gossens U. Heinkel Institute for Computer Aided Circuit Design University of Erlangen Nuremberg Erlangen Germany Department of Computer Science III University of Erlangen Nuremberg Erlangen Germany Lucent Technologies Inc. Nuremberg Germany

This paper presents our approach to leverage formal methods in an industrial design environment by closing the gap between the specification and design phases. We achieve this goal by deriving behavioural VHDL models ... 详细信息

关键词： Formal specifications Application specific integrated circuits Systems engineering and theory Natural languages circuit synthesis computer science computer industry Mathematical model Mathematical analysis Electronics industry

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Embedded systems verification with FGPA-enhanced in-circuit emulator

Embedded systems verification with FGPA-enhanced in-circuit ...

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International Symposium on System Synthesis

作者： M. Meerwein C. Baumgartner T. Wieja W. Glauert Automotive Equipment Division 8 Robert Bosch GmbH Reutlingen Germany Institute for Computer Aided Circuit Design University of Erlangen Nuremberg Erlangen Germany

ISBN: (纸本)0769507654

We present a novel coverification concept for embedded microcontrollers that satisfies industrial requirements. Based on a commercially available CPU in-circuit emulator coupled with FPGA boards, it verifies the correctness of an implementation in terms of function and timing within a real-world environment. Using our system, the software engineer can write, test and optimize programs for a chip that is not yet physically existent. In addition the system is used to obtain software module characterization data required for system partitioning. Its ability to integrate analog circuitry enables verification of the complete system-on-chip. Our methodology is fully integrated into the ASIC design flow providing ease of use and a high level of verification accuracy.

关键词： Embedded system Microcontrollers Field programmable gate arrays Timing Software systems Systems engineering and theory circuit testing Software testing System testing System-on-a-chip

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Linking codesign and reuse in embedded systems design 00

Linking codesign and reuse in embedded systems design

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Proceedings of the eighth international workshop on Hardware/software codesign

作者： M. Meerwein C. Baumgartner W. Glauert Robert Bosch Gmbh Automotive Equipment Division 8 72703 Reutlingen Germany Institute for Computer Aided Circuit Design University of Erlangen-Nuremberg 91058 Erlangen Germany

ISBN: (纸本)9781581132687

This paper presents a complete codesign environment for embedded systems which combines automatic partitioning with reuse from a module database. Special emphasis has been put on satisfying the requirements of industrial design practice and on the technical and economic constraints associated with automotive control applications. The object-oriented database architecture allows efficient management of a large number of modules. Experimental results from a real-world example demonstrate the viability and advantages of the presented methodology.

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LayDis - An advanced navigation system for electron beam probing

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MICROELECTRONIC ENGINEERING 1996年第1-4期31卷 355-362页

作者： Kuntzsch, C Goldbach, M Wolz, W Fraunhofer Institute of Integrated Circuits FhG IIS-A Department of Applied Electronics Am Weichselgarten 3 91058 Erlangen Germany Tel.: x49 9131 776 443 University of Erlangen-Nürnberg Institute of Computer-Aided Circuit Design Prof. Dr. W. H. Glauert Cauerstr. 6 91058 Erlangen Germany Tel.: x49 9131 858680

This paper presents a new tool set called LayDis providing advanced navigation support for chipinternal probing. Although the tool set has been designed primarily for electron beam test equipment (EBT), it is extendable to support optical beam test equipment, contacting prober stations, focused ion beam stations (FIB), or laser cutters. The new navigation system has got multiple links to the CAD-data, and its main advantage comes from the fact that layout navigation can be performed even if nothing else but layout data (GDS II file) is available. The user is guided by the system through all stages of pre-processing the design data. The software has built-in features for automatic probing point selection based on technology-proprietary selection rules. An unique built-in feature is the full support of layout navigation based on text information contained in a layout file. To support complete netlist-driven navigation for fault localisation purposes a pre-processor is available to use Dracula LVS results for the crossmapping of netlist naming information and layout polygon description. In addition, LayDis is capable of generating and processing probing point list files for the repeated operation of the same verification and measurement tasks. This feature enables the design&Test engineer to verify or characterise several identical devices during the process of 'First Silicon characterisation'.

关键词： Integrated circuit testing

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NEURAL-NETWORK APPROACH TO THE SOLUTION OF LINEAR COMPLEMENTARITY-PROBLEMS

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INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS 1995年第6期8卷 431-445页

作者： OSOWSKI, S Institute of the Theory of Electrical Engineering and Electrical Measurements Technical University Warsaw Poland Stanislaw Osowski was born in Poland in 1948. He received the Dipl. Ing. Dr. Ing. and Dr Ing. Habil. degrees from the Technical University of Warsaw Poland in 1972 1975 and 1981 respectively all in electrical engineering. At present he is a professor at the Institue of Theory of Electrical Engineering and Electrical Measurements Technical University of Warsaw. His research and teaching interests are in the area of neural networks optimization techniques and computer-aided circuit analysis and design.

The paper presents the application of nonlinear neural optimization networks to solve the linear complementarity problem. Two different approaches are presented and investigated: one leading to linear and the second t... 详细信息

关键词： Neural networks

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