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17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2024

作者： Liu, Shuang Radetzki, Martin University of Stuttgart Institute of Computer Architecture and Computer Engineering Stuttgart Germany

ISBN: (纸本)9798331530471

Network-on-Chip (NoC) offers a promising solution for on-chip communication in highly integrated System-on-Chips (SoCs). NoCs can be designed with either regular or application-specific network topologies. While regular topologies are easy to design, they are not ideal for systems with heterogeneous processing elements (PEs) that vary in size. The design of application-specific NoCs, however, involves several interrelated problems that impact each other. This work addresses the challenges in the synthesis of application-specific NoCs by proposing an Integer Linear Programming (ILP) framework. This framework enables the co-design of major problems, including floorplanning, routing topology generation, routing path construction, and application mapping. Although the ILP framework can be applied to each problem individually or in a stepwise manner, the co-design of these interconnected problems allows synthesis steps to interact, enabling designers to explore the entire design space. Using this framework, we have analyzed various design configurations in the synthesis of application-specific NoCs. © 2024 IEEE.

关键词： Network-on-chip

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Integer Linear Programming Based Design of Deadlock-Free Routing for Chiplet-Based Systems 37

Integer Linear Programming Based Design of Deadlock-Free Rou...

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37th IEEE International System-on-Chip Conference, SOCC 2024

作者： Liu, Shuang Radetzki, Martin University of Stuttgart Embedded Systems Institute of Computer Architecture and Computer Engineering Stuttgart Germany

ISBN: (纸本)9798350377569

Chiplet-based systems have become prominent in large Systems-on-Chips (SoCs) as a means to mitigate increasing design costs. However, the integration of multiple chiplets introduces new challenges in the interconnection network, potentially leading to deadlocks. In this paper, we propose an Integer Linear Programming (ILP) based design approach to address this issue. Our method considers various design factors for deadlock-free routing, such as topology, latency, load balancing, path diversity, and fault tolerance, applicable to both general-purpose chiplets and application-specific chiplets. It facilitates the determination of optimal turn restrictions for general-purpose chiplets or constructs optimal deadlock-free routing paths for application-specific chiplets if the communication patterns are known. The results demonstrate the capability of the method to find optimal solutions under various design considerations. © 2024 IEEE.

关键词： Integer linear programming

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Optimized Detection of Marginal Defects in Standard Cells Using Unsupervised Learning 33

Optimized Detection of Marginal Defects in Standard Cells Us...

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33rd IEEE Asian Test Symposium, ATS 2024

作者： Pandaram, Karthik Amrouch, Hussam Polian, Ilia University of Stuttgart Institute of Computer Engineering and Computer Architecture Germany Germany

ISBN: (纸本)9798331529161

Marginal defects, such as high-resistance short or low-resistance open defects, are hard to detect by conventional pass-fail test methods because their manifestations are practically indistinguishable from the effects of regular variations. However, their coverage is essential for circuits with high-quality requirements and/or when early-life failures are a concern. In this paper, we propose an alternative detection concept based on evaluating several parametric responses of a circuit against a machine learning (ML) model. We use a 14nm FinFET transistor model validated against industrial measurements. We show that high detection performance is possible even when unsupervised learning that does not consider defective behavior is used;to this end, the procedure is generic. Moreover, an AUC score of over 0.96 is achieved when only measurements from a single voltage level are utilized, in contrast to earlier work. We also present a procedure to select a reduced set of test sequences, achieving an improvement of 50% reduction with a limited impact on detection performance. © 2024 IEEE.

关键词： Unsupervised learning

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A Study on Efficiency Improvements of DNN Accelerators via Denormalized Arithmetic Elimination 38

A Study on Efficiency Improvements of DNN Accelerators via D...

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38th International Conference on VLSI Design, VLSID 2025

作者： Kharitonov, Alexander Kundu, Sandip Institute of Computer Architecture & Computer Engineering University of Stuttgart Stuttgart Germany University of Massachusetts Department of Electrical & Computer Engineering Amherst United States

ISBN: (纸本)9798331522445

Deep Neural Networks (DNNs) excel in tasks such as vision and speech processing, driving their widespread use. A key operation in DNNs is convolution, which is often implemented using General Matrix Multiplication (GEMM). Modern CPUs incorporate hardware accelerators for faster GEMM operation. Reduced precision floating-point (RPF) formats such as bfloat16 and TensorFloat32 are popular in machine learning, offering a balance between classification accuracy, dynamic range for training gradients, and hardware efficiency compared to traditional IEEE 754 32-bit or 64-bit floating-point numbers. While RPF is well-studied in the context of DNNs, a major complexity arises from handling denormalized numbers. This paper investigates their impact on DNNs and finds that removing denormalized number support from hardware accelerators does not affect classification accuracy, while allowing significant improvements in hardware efficiency and performance. With proliferation of data centers to accommodate the growing number of DNN applications, power reductions at the GEMM level can significantly improve cluster-wide efficiency, promoting sustainability. Our results indicate that eliminating denormalized arithmetic leads to significant improvements in multiplier circuit efficiency, with reductions of up to 46% in area (LUT count), 28% in longest path delay, and 59% in power consumption, all while maintaining DNN classification accuracy. © 2025 IEEE.

关键词： Deep neural networks

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Fault Tolerance in Stochastic Circuits for Recurrent Sequential Neural Networks 33

Fault Tolerance in Stochastic Circuits for Recurrent Sequent...

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33rd IEEE Asian Test Symposium, ATS 2024

作者： Sengupta, Roshwin Polian, Ilia Hayes, John P. University of Stuttgart Institute of Computer Architecture and Computer Engineering Stuttgart Germany University of Michigan Computer Engineering Laboratory Ann ArborMI United States

ISBN: (纸本)9798331529161

Stochastic computing (SC) provides low-area, power-efficient hardware solutions suitable for edge systems, but its scalability poses challenges due to its precision limitations, especially in noisy environments. This paper investigates the fault tolerance of key SC components, such as stochastic number generators (SNGs) and activation functions (AFs), within recurrent and sequential networks like long short-term memory (LSTM) networks. We inject bit-flip faults into a network's most sensitive inputs, weights and AFs, and study fault propagation across different network layers. Our findings reveal that SC component choices significantly influence fault tolerance. For example, networks using Sobol-based SNGs with tanh AFs exhibited stronger resilience than those with LFSR-based SNGs and ReLU AFs, by maintaining higher accuracy under fault conditions. However, the accuracy of the networks declined significantly under simultaneous faults in inputs, weights and AFs. Additionally, while increasing stochastic number lengths improved fault tolerance, they also increased latency. Nevertheless, the SC networks achieved up to 54% area and 72% power savings, making them ideal for resource-constrained applications. We also found that there is a trade-off between efficiency and fault tolerance: SC designs that focus on resource efficiency may struggle in noisy environments, where fault-tolerant SC designs are more effective. This implies that fault resilience in SC architectures depend heavily on design choices and cannot be assumed inherent across all configurations. © 2024 IEEE.

关键词： Long short-term memory

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Pattern Generation for Efficient Acceptability Verification of Approximate Circuits

Pattern Generation for Efficient Acceptability Verification ...

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2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024

作者： Chao, Wei-Ji Kourfali, Alexandra Lylina, Natalia Wu, Jun-Tsung Yang, Jing-An Wang, Chih-Hao Hsieh, Tong-Yu Wunderlich, Hans-Joachim National Sun Yat-sen University Department of Electrical Engineering Taiwan Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany

ISBN: (纸本)9798350360349

Approximate computing allows designers to trade-off precision with hardware cost and power consumption. The possible degree of approximation relies on a realistic quality assessment with functional input sequences and metrics to quantify the error magnitude. The complete exploration of the input space is impracticable in most cases but a partial input sequence might underestimate the severity of possible errors. The paper at hand presents an approach to generate patterns for efficient acceptability verification of an approximate circuit and to complement conventional quality assessment methods. A modified miter design indicates the differences between the approximate and the precise circuit, and an existing ATPG flow is used to maximize the differences. A case study on JPEG2000 decoder validates that our approach can efficiently and effectively identify unacceptable approximate results where conventional image quality assessment methods failed. © 2024 IEEE.

关键词： Timing circuits

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Large Language Model-Based Optimization for System-Level Test Program Generation 37

Large Language Model-Based Optimization for System-Level Tes...

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37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024

作者： Schwachhofer, Denis Domanski, Peter Becker, Steffen Wagner, Stefan Sauer, Matthias Pfluger, Dirk Polian, Ilia Institute of Computer Engineering and Computer Architecture University of Stuttgart Stuttgart Germany Institute of Software Engineering University of Stuttgart Stuttgart Germany Institute for Parallel and Distributed Systems University of Stuttgart Stuttgart Germany Technical University of Munich Heilbronn Germany Advantest Europe Boeblingen Germany

ISBN: (纸本)9798350366884

System-Level Test (SLT) is essential for testing integrated circuits, focusing on functional and non-functional properties of the Device under Test (DUT). Traditionally, test engineers manually create tests with commercial software to simulate the DUT's end-user environment. This process is both time-consuming and offers limited control over non-functional properties. This paper proposes Large Language Models (LLMs) enhanced by Structural Chain of Thought (SCoT) prompting, a temperature schedule, and a pool of previously generated snippets to generate high-quality code snippets for SLT. We repeatedly query the LLM for a better snippet using previously generated snippets as examples, thus creating an iterative optimization loop. This approach can automatically generate snippets for SLT that target specific non-functional properties, reducing time and effort. Our findings show that this approach improves the quality of the generated snippets compared to unstructured prompts containing only a task description. © 2024 IEEE.

关键词： Functional Test Large Language Models Optimization System-Level Test Test Generation

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Exploring Gate-Diversity Enabled by Reconfigurable Memristive Technology 30

Exploring Gate-Diversity Enabled by Reconfigurable Memristiv...

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30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023

作者： Brandhofer, Sebastian Chen, Ziang Chen, Li-Wei Zhao, Xianyue Du, Nan Polian, Ilia University of Stuttgart Institute of Computer Architecture and Computer Engineering Stuttgart Germany Friedrich Schiller University Jena Institute for Solid State Physics Jena Germany Department of Quantum Detection Jena Germany

ISBN: (纸本)9798350326499

While memristive devices are highly attractive as memory cells, they are also capable of performing computations, paving the way to futuristic in-memory computing architecture. Several memristive logic families have been proposed, and approaches to map gate-level logic circuits to such memristive implementations have been introduced. In this paper, we focus on the CRS logic family that offers several advantages compared to the more often considered IMPLY and MAGIC families. A central feature of CRS is the ability of one physical memristive device to realize varying logic gates over several clock cycles. Our method computes a schedule, i.e., an assignment which logic gate of a given circuit is executed on which memristive device during which clock cycles. Using an optimal MaxSAT model, it can minimize the resulting schedule's duration (depth), the cost of the used memristors, or the cost of additional cache register cells, while satisfying all dependencies needed for correct computation. In addition to results of the scheduling procedure itself, we report a physical experiment that demonstrates one of the schedules and discuss the energy benefits of the CRS family. © 2023 IEEE.

关键词： Logic gates

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Pedestrian wind flow prediction using spatial-frequency generative adversarial network

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Building Simulation 2024年第2期17卷 319-334页

作者： Pengyue Wang Maozu Guo Yingeng Cao Shimeng Hao Xiaoping Zhou Lingling Zhao School of Architecture and Urban Planning Beijing University of Civil Engineering and ArchitectureBeijing100044China Beijing Key Laboratory of Intelligent Processing for Building Big Data Beijing100044China School of Electrical and Information Engineering Beijing University of Civil Engineering and ArchitectureBeijing100044China School of Computer Science and Technology Harbin Institute of TechnologyHarbin150001China

Pedestrian wind flow is a critical factor in designing livable residential environments under growing complex urban *** pedestrian wind flow during the early design stages is essential but currently suffers from inefficiencies in numerical *** learning,particularly generative adversarial networks(GAN),has been increasingly adopted as an alternative method to provide efficient prediction of pedestrian wind ***,existing GAN-based wind flow prediction schemes have limitations due to the lack of considering the spatial and frequency characteristics of wind flow *** study proposes a novel approach termed SFGAN,which embeds spatial and frequency characteristics to enhance pedestrian wind flow *** the spatial domain,Gaussian blur is employed to decompose wind flow into components containing wind speed and distinguished flow edges,which are used as the embedded spatial *** information of wind flow is obtained through discrete wavelet transformation and used as the embedded frequency *** spatial and frequency characteristics of wind flow are jointly utilized to enforce consistency between the predicted wind flow and ground truth during the training phase,thereby leading to enhanced *** results demonstrate that SFGAN clearly improves wind flow prediction,reducing Wind_MAE,Wind_RMSE and the Fréchet Inception Distance(FID)score by 5.35%,6.52%and 12.30%,compared to the previous best method,*** also analyze the effectiveness of incorporating the spatial and frequency characteristics of wind flow in predicting pedestrian wind *** reduces errors in predicting wind flow at large error intervals and performs well in wake regions and regions surrounding *** enhanced predictions provide a better understanding of performance variability,bringing insights at the early design stage to improve pedestrian wind *** proposed spatial-frequen

关键词： pedestrian wind flow prediction generative adversarial network Gaussian kernel wavelet transform objective function

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A Study on Efficiency Improvements of DNN Accelerators via Denormalized Arithmetic Elimination

A Study on Efficiency Improvements of DNN Accelerators via D...

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International Conference on VLSI Design

作者： Alexander Kharitonov Sandip Kundu Institute of Computer Architecture & Computer Engineering University of Stuttgart Stuttgart Germany Department of Electrical & Computer Engineering University of Massachusetts Amherst USA

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

关键词： Training Accuracy Power demand Artificial neural networks Very large scale integration Delays Table lookup Sustainable development Speech processing Hardware acceleration

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