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作者： Bille, Philip Landau, Gad M. Raman, Rajeev Sadakane, Kunihiko Satti, Srinivasa Rao Weimann, Oren DTU Informatics Technical University of Denmark Denmark Department of Computer Science University of Haifa Israel Department of Computer Science University of Leicester United Kingdom National Institute of Informatics Japan School of Computer Science and Engineering Seoul National University Korea Republic of Department of Computer Science and Applied Mathematics Weizmann Institute of Science Israel Department of Computer Science and Engineering NYU-Poly United States

ISBN: (纸本)9780898719932

Let 5 be a string of length N compressed into a context-free grammar S of size n. We present two representations of S achieving O(logN) random access time, and either O(n · αk(n)) construction time and space on the pointer machine model, or 0(n) construction time and space on the RAM. Here, αk(n) is the inverse of the kth row of Ackermann's function. Our representations also efficiently support decompression of any substring in S: we can decompress any substring of length m in the same complexity as a single random access query and additional O(m) time. Combining these results with fast algorithms for uncompressed approximate string matching leads to several efficient algorithms for approximate string matching on grammar-compressed strings without decompression. For instance, we can find all approximate occurrences of a pattern P with at most k errors in time O(n(min(|P|k,k4 + |P|) + logN) + occ), where occ is the number of occurrences of P in S. Finally, we are able to generalize our results to navigation and other operations on grammar-compressed trees. All of the above bounds significantly improve the currently best known results. To achieve these bounds, we introduce several new techniques and data structures of independent interest, including a predecessor data structure, two "biased" weighted ancestor data structures, and a compact representation of heavy-paths in grammars.

关键词： Data structures

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Enhancement of Adaptive Software-Based Self Test Generation of Embedded Processors Cores

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IFAC-PapersOnLine 2019年第27期52卷 56-61页

作者： Ján Hudec Institute of Computer Engineering and Applied Informatics Faculty of Informatics and Information Technologies Slovak University of Technology 84216 Bratislava Slovakia

The paper deals with automatic software-based test generation for processors as basic blocks of current complex systems on chip and embedded systems. Testing processors needs continually new test generation methods, algorithms and test application techniques for their verification, manufacture and infield testing and reliable life-time run. The functional tests of processors are mainly generated over an instruction set architecture and processor model description. Such types of tests are serving as additional tests to structural testing or as tests used in verification. They run in similar form and frequency as real programmes. Such tests are categorized as the software-based self tests. A metric for quality evaluation of the software-based tests is obviously provided by code coverage of a processor model. A functional test generation method is based on VHDL model of processors and genetic algorithms with using various evolutionary strategies. The contribution to the SBST methods based on GAs using the latest defined ES was identified. Functionality and effectiveness of the developed methods were evaluated in the implemented system AGenMIX with enhanced function of genetic algorithms computation over three types of RISC processor.

关键词： Processor functional test generation software-based self test genetic algorithms evolutionary strategies VHDL code coverage fitness function test simulation verification validation

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Image based touristic monument classification using Graph Based Visual Saliency and Scale-Invariant Feature Transform

Image based touristic monument classification using Graph Ba...

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IASTED International Conference on computer Graphics and Imaging, CGIM 2012

作者： Kalliatakis, Grigorios E. Kounalakis, Tsampikos Papadourakis, Georgios Triantafyllidis, Georgios A. Applied Informatics and Multimedia Dept. Technological Educational Institute of Crete Heraklion Greece Dept. of Electronic and Computer Engineering School of Engineering and Design Brunei University London United Kingdom

ISBN: (纸本)9780889869219

This paper presents an image-based application using Graph Based Visual Saliency (GB VS) and Scale-Invariant Feature Transform (SIFT), aiming at simple image classification of well-known touristic monuments in the geographic area of Heraklion, Crete, Greece. For this purpose, photographs taken at various sites of interest are being compared to an existing database containing photos of these sites at different angles and zoom. The time required in such application is an important element. To this goal, the proposed application employs SIFT algorithm to compare the user-taken photographs with the database photographs, that have been previously processed according to the Graph Based Visual Saliency technique, in order to minimize the "noise" of the monument's background and keep only the SIFT features that will help faster and more accurate classification. The application is then able to classify these photographs fast, helping the user to better understand what he sees and in which area he had this photograph.

关键词： Image classification

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A new colluded adversarial VNet embeddings attack in cloud 18

A new colluded adversarial VNet embeddings attack in cloud

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18th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2017

作者： Liu, I-Hsien Fang, Tay-Jiun Li, Jung-Shian Sun, Meng-Wei Liu, Chuan-Gang Institute of Computer and Communication Engineering National Cheng Kung University Tainan Taiwan Department of Applied Informatics and Multimedia Chia-Nan University of Pharmacy and Science Tainan Taiwan

ISBN: (纸本)9781538631515

Nowadays, network virtualization has been widely investigated in order to prevent Internet ossification, and develop future emerging network applications flexibly. However, prior work by Pignolet et al. shows the possible attacking methodology with which the attackers can disclose the whole cloud topology while deploying virtual networks in cloud named Topology Disclosure Attack. In this attack model, the attacker pretends to deploy virtual networks in cloud by issuing the graph requests to service provider. And the service provider responds the requests to the attacker after examining his/her topology resources. With this request/reply model, Pignolet et al. believe this attack eventually infers the targeted topology. However, one vital reason leads this attack to the failure- too many virtual requests from one adversary in a time. This paper tries to provide a new topology disclosure attack model, which multiple attackers launch attacks at the same time with the assistance of proposed Query-Trie and network tomography technique. Hence, in this paper, we propose much more possible attack model in cloud and this topic also encourages the network researchers to develop resistance mechanism against it in the future. © 2017 IEEE.

关键词： Topology

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Development and implementation of a Network Processor architecture in reconfigurable logic (FPGA)

Development and implementation of a Network Processor archit...

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2010 8th IEEE Workshop on Intelligent Solutions in Embedded Systems, WISES 2010

作者： Constantinos, Stefanatos Papaefstathiou, Ioannis Charalampos, Manifavas Electronic and Computer Engineering Dept Technical University of Crete Chania Crete Greece Applied Informatics and Multimedia Dept Technological Educational Institute of Crete Heraklion Crete Greece

ISBN: (纸本)9781424457168

Network Processors are used at the core of the Internet, providing routers, switches and other essential network devices with the necessary processing power to deliver proper data forwarding and other network related functions (VoIP, security, etc.) at the required level of performance. In this paper, we present a Network Processor architecture, designed to support all the fundamental instructions needed to deliver proper frame processing. It is designed and implemented on a specific FPGA board, employing Xilinx's Virtex-5, in order to allow for rapid deployment and usage. Apart from the architecture's description, performance measurements are provided that demonstrate the architecture's capabilities. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Security Protection with Dynamic Assigned Address Mechanism in Industrial Control Systems

Security Protection with Dynamic Assigned Address Mechanism ...

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2020 ACM International Conference on Intelligent Computing and its Emerging Applications, ICEA 2020

作者： Liu, Chuan-Gang Wu, Chin-Jui Liu, I-Hsien Wu, Chi-Che Li, Jung-Shian Department of Applied Informatics and Multimedia Chia-Nan University of Pharmacy and Science Tainan Taiwan Department of Electrical Engineering Institute of Computer and Communication Engineering National Cheng Kung University Tainan Taiwan

ISBN: (纸本)9781450383042

In recent years, industrial control systems (ICS) are widely used in many occasions, which makes information security of ICS an important issue. This study discusses the communication and management on ICS to make ICS intelligent. We proposed a method to avoid attack of communication, and elaborated the means of our proposed communication in which all communication parties communicate with each other without transmitting IP information. Moreover, as an intelligent ICS, the transmission module we design can detect anomaly in the system and change the transmission rule based on our algorithm, also known as a type of moving target defense. Therefore, we proposed the scheme to improve the transmission security in ICS. The experimental results also show that our scheme can be feasible in ICS. © 2020 ACM.

关键词： Intelligent systems

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Differential Privacy Protection with Group Onion Routing based on AI-based URL Classification

Differential Privacy Protection with Group Onion Routing bas...

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2020 ACM International Conference on Intelligent Computing and its Emerging Applications, ICEA 2020

作者： Liu, I-Hsien Chang, Yung-Lin Li, Jung-Shian Liu, Chuan-Gang Department of Electrical Engineering Institute of Computer and Communication Engineering National Cheng Kung University Tainan Taiwan Department of Applied Informatics and Multimedia Chia-Nan University of Pharmacy and Science Tainan Taiwan

ISBN: (纸本)9781450383042

Due to the rapid spread of tablet computers, smartphones, and other mobile information devices, wireless communication technology is fully developed and deployed widely. Mobile Internet access has been a main and important way to communicate the world in daily and it privacy protection also catches much attentions. The Onion Router, better known as Tor, is a technique for anonymous communication over internet without regional restrictions for privacy protection. Apart from this, Tor can reach sites that normal search engine cannot search. As the opinion of Tor, the transmitted data has been encrypted layer by layer, just like onion, before it reaching server. Our research proposed a system predicting URL's category with the use of machine learning technique before visiting. According to the category prediction, we represent different privacy level with three kinds of RSA key lengths on onion routing. Depending on various situations, our system can obtain the balance between security and time cost. Hence, our proposed scheme can make onion routing more flexible and efficiently. © 2020 ACM.

关键词： Machine learning

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Fast 3D scene object detection and real size estimation using Microsoft Kinect sensor

Fast 3D scene object detection and real size estimation usin...

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IASTED International Conference on computer Graphics and Imaging, CGIM 2012

作者： Demetriou, Michael K. Kounalakis, Tsampikos Vidakis, Nikolaos Triantafyllidis, Georgios A. Applied Informatics and Multimedia Dept. Technological Educational Institute of Crete Heraklion Greece Dept. of Electronic and Computer Engineering School of Engineering and Design Brunei University London United Kingdom

ISBN: (纸本)9780889869219

This paper presents an efficient and fast system for object detection in a 3D scene using the capabilities of Microsoft Kinect sensor in depth map generation. Besides, the proposed method introduces a real size estimation of the detected objects. Successful 3D scene's object detection and real size calculation are crucial features in computer vision to the goal of making machines that see objects like humans do. In our system we employ effective depth map processing techniques, along with edge detection, connected components detection and filtering approaches, in order to design a complete algorithm for efficient object detection and real size calculation, even in complex scenes with many objects. Experimental results on three different 3D scenes are presented, showing the efficiency of the proposed design.

关键词： Image segmentation

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Measurement of vibration mode structure for adaptive vibration suppression system by digital holography

Measurement of vibration mode structure for adaptive vibrati...

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2013 Joint IEEE International Symposium on Applications of Ferroelectric and Workshop on Piezoresponse Force Microscopy, ISAF/PFM 2013

作者： Psota, Pavel Lédl, Vít Doleček, Roman Mokrý, Pavel Kopecký, Václav TOPTEC Institute of Plasma Physics Turnov Czech Republic Institute of Mechatronics and Computer Engineering TU Liberec Liberec Czech Republic Institute of Novel Technologies and Applied Informatics TU Liberec Liberec Czech Republic

关键词： Vibration measurement

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Efficient Time-Delay System Optimization with Auto-Configured Metaheuristics

Efficient Time-Delay System Optimization with Auto-Configure...

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2023 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2023

作者： Senkerik, Roman Byrski, Aleksander Guzowski, Hubert Janku, Peter Kadavy, Tomas Oplatkova, Zuzana Kominkova Matusu, Radek Pluhacek, Michal Pekar, Libor Smolka, MacIej Viktorin, Adam Tomas Bata University A.I. Lab Faculty of Applied Informatics Department of Informatics and Artificial Intelligence Zlin Czech Republic Tomas Bata University Faculty of Applied Informatics Department of Automation and Control Engineering Zlin Czech Republic Institute of Computer Science Agh University of Science and Technology Krakow Poland

ISBN: (纸本)9798350337020

This paper presents an experimental study that compares the performance of four selected metaheuristic algorithms for optimizing a time delay system model. Time delay system models are complex and challenging to optimize due to their inherent characteristics, such as non-linearity, multi-modality, and constraints. The study includes an explanation of the choice and core functionality of the selected algorithms, which are both baseline and state-of-the-art variants of self-organizing migrating algorithm (SOMA), state-of-the-art variant from the Success-History-based Adaptive Differential Evolution family of algorithms, with emphasis on diverse search (DISH algorithm), and Covariance Matrix Adaptation Evolution Strategy (CMA-ES) algorithm. The hyperparameters of the metaheuristic algorithms were set using the iRace automatic algorithm configuration framework. The paper emphasizes the importance of metaheuristic algorithms in control engineering for time-delay systems to develop more effective and efficient control strategies and precise model identifications. The experimental results highlight the effectiveness of the state-of-the-art algorithms with specific adaptive mechanisms like population organization process, diverse search and adaptation mechanisms ensuring a gradual transition from exploration to exploitation. Overall, this study contributes to understanding the challenges and advantages of using metaheuristic algorithms in control engineering for time delay systems. The results provide valuable insights into the performance of modern metaheuristic algorithms and can help guide the selection of appropriate adaptive mechanisms of metaheuristics. © 2023 IEEE.

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