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REASONING ON THE LOCATION OF COMPONENTS FOR ASSEMBLY PACKAGING

JOURNAL OF MECHANICAL design 1991年第4期113卷 402-407页

作者： KIM, JJ GOSSARD, DC T. J. Watson Research Center Interactive Geometric Modeling IBM Research Division Yorktown NY 10598 Computer-Aided Design Laboratory Department of Mechanical Engineering Massachusetts Institute of Technology Cambridge MA 02139

The process of locating components in an available space while satisfying spatial relationships among the components is called packaging. The task requires extensive spatial reasoning about geometric shapes. It is a generic design task common to many domains. It is also very time-consuming, especially as machines become more compact and complex. This paper describes progress toward automation of the packaging problem. An approach is proposed to determine the optimal locations of components in an assembly from spatial relationships between the components. The approach utilizes a novel combination of optimization and solid modeling techniques.

关键词： Machinery Optimization Solid modeling Packaging design Shapes Manufacturing

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Deformable curve and surface finite-elements for free-form shape design 91

Deformable curve and surface finite-elements for free-form s...

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18th Annual Conference on computer graphics and Interactive Techniques, SIGGRAPH 1991

作者： Celniker, George Gossard, Dave Schlumbergcr Laboratory for Computer Science AustinTX78720 United States Department of Mechanical Engineering Computer Aided Design Laboratory Massachusetts Institute of Technology 77 Massachusetts Ave CambridgeMA02139 United States

ISBN: (纸本)0897914368

The finite element method is applied to generate primitives that build continuous deformable shapes designed to support a new free-form modeling paradigm. The primitives autonomously deform to minimize an energy functional subject to user controlled geometric constraints and loads. The approach requires less user input than conventional free-form modeling approaches because the shape can be parameterized independently of the number of degrees of freedom needed to describe the shape. Both a curve and a surface finite element arc developed. The properties of these geometric primitives have been engineered to support an interactive three phase approach for defining very fair free-form shapes as found in automobiles, ship hulls and car bodies. The shape's character lines or folds and edges are defined with deformable curve segments. These character lines are then "skinned" with a deformable surface. The final shape is sculpted interactively by applying loads to the surface to control the surface shape between character lines. Shapes created with this technique enjoy the advantage that they are already meshed for further finite element analysis. © 1991 ACM.

关键词： Finite element method

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Orientation and insertion of randomly presented parts using vibratory agitation

Orientation and insertion of randomly presented parts using ...

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ASME 1991 design Technical Conferences, DETC 1991

作者： Moncevicz, Paul H. Jakiela, Mark J. Ulrich, Karl T. Department of Mechanical Engineering Massachusetts Institute of Technology Computer-Aided Design Laboratory CambridgeMA United States Massachusetts Institute of Technology Sloan School of Management CambridgeMA United States

ISBN: (纸本)9780791807491

In this article, we propose a new approach to automated assembly. Currently, automated assembly is expensive and difficult because all of the machines required for its implementation impose organization on the parts being assembled. It is this organization that is costly. We investigate an approach that requires less organization and results in assembly as a bulk process. We describe an initial implementation of this approach with a particular parts presentation system. Experiments are performed to determine the part characteristics that promote the success of the implementation. The experimental results are described and future work is suggested. © 1991 American Society of Mechanical Engineers (ASME). All rights reserved.

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An algorithm for discrete event logic simulation on distributed systems

An algorithm for discrete event logic simulation on distribu...

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1991 IEEE Region 10 International Conference on EC3-Energy, computer, Communication and Control Systems, TENCON 1991

作者： Sundaram, S. Mohan, T.S. Patnaik, L.M. Indian Institute of Science Bangalore560 012 India Computer Aided Design Laboratory India Supercomputer Education and Research Centre Knowledge Based Computer System Laboratory India Supercomputer Education and Research Centre Dept. of Computer Science and Automation Microprocessor Applications Laboratory India

ISBN: (纸本)0780305388

Increase in the complexity of VLSI digital circuit design demands faster logic simulation techniques than those currently available. One of the ways of speeding up existing logic Simulation Agorithms is by exploiting the inherent parallelism of the sequential version. In this paper, we explore the possibility of mapping an event driven logic simulation algorithm onto a cluster of processors interconnected by an ethernet. The set of events at any simulation time. step is partitionecl by the Master Task (running on the host processor) anlong the Worker Tasks(running of the other processor's). The partitioning scheme ensures a balanced load. Each Worker Task determines the fanout, elementts, evaluates them independently and comes up with the new event list which is passed onto the Master Task. After receiving the event lists from all the workers, the Master Task increments the simulation time step, computes the new event list partition for the next simulation cycle. We have implemented this distributed logic simulation algorithm on a set of 8 VAXstations using CT - A package for distributed programming. The paper concludes with a note on the speedup figures obtained on the ISCAS benchmark circuits. © 1991 IEEE.

关键词： computer circuits

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Parallel processing of a multilayer routing package

Parallel processing of a multilayer routing package

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IEEE Region 10 International Conference TENCON

作者： M.K. Srinivas T. Radhakrishnan Computer Aided Design Laboratory Indian Institute of Technology Bangalore India

With the increasing density of components on Printed Circuit Boards (PCBs) and the advance ment of fabrication technologies for multilayer PCBs, improvement of speed and techniques for the computer aided design of multilayer PCBs has be come a major area of research. The paper discusses the parallel processing of layering and routing algorithms for design of multilayer PCBs on a network of small computers with a moderately high speed communication medium. Multilayer PCB design consists in partitioning a netlist into as many layers as necessary, and routing one or two layersat a time. The routing processes of the different netlists is entirely independent of each other.

关键词： Parallel processing Nonhomogeneous media Routing Packaging Wires Local area networks Costs Ethernet networks Fabrication Wiring

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AN APPROACH TO CHIP-INTERNAL CURRENT MONITORING AND MEASUREMENT USING AN ELECTRON BEAM TESTER

AN APPROACH TO CHIP-INTERNAL CURRENT MONITORING AND MEASUREM...

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IEEE International Test Conference

作者： K. Helmreich P. Nagel W. Wolz K.D. Muller-Glaser Institute for Computer Aided Circuit Design University Erlangen-Nuünberg Germany

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Pseudoedge: A hierarchical skeletal modeler for the design of structural components

Pseudoedge: A hierarchical skeletal modeler for the design o...

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ASME 1991 design Technical Conferences, DETC 1991

作者： Bonner, David L. Jakiela, Mark J. Watanabe, Masaki Department of Mechanical Engineering Computer-Aided Design Laboratory Massachusetts Institute of Technology CambridgeMA United States Scientific Research Laboratory Central Engineering Laboratories Nissan Motor Company Limited Yokosuka Japan

ISBN: (纸本)9780791897768

A new design model for the creation of mechanical components has been developed. In this model, the shape is expressed by its areas of prominence or maximum curvature, for which we use the term pseudoedges. In terms of traditional design, these represent both fillet, chamfer and intersection lines, and more general shape features. The pseudoedges of the model combine with a skeletal shape that is used as a starting form, thereby creating a hierarchy of geometric dependencies that affords both global and local control. The surface is represented by a quilt of parametric Bezier patches, with tangent plane continuity everywhere and only certain isolated singularities. Considerable degrees of deformation are possible, with predictable control and at small computational expense;there is no need for computation of intersections or parameter space trimming of patches. © 1991 American Society of Mechanical Engineers (ASME). All rights reserved.

关键词： Machine design

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Estimating essential design characteristics to support project planning for ASIC design management

Estimating essential design characteristics to support proje...

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IEEE International Conference on computer-aided design

作者： K.D. Muller-Glaser K. Kirsch K. Neusinger Institute of Computer-Aided Circuit Design University Erlangen-Nuünberg Erlangen Germany

To enhance project planning and feasibility study for ASIC (application-specific integrated circuit) design, a chip estimation system (CES), tightly coupled with a project plan generator system (PGS) has been developed. The CES calculates chip area, speed, and power dissipation from data of a knowledge-based data acquisition system which gathers basic design characteristics, requirement specification data, and information about complexity and problems of a design. The resulting data are transferred to the PGS, which generates alternative project plans based on a design-style-specific knowledge base. Using vendor- and technology-specific cost factors, estimation of design time and design, production, and test costs is performed. The project-control system controls execution of a selected project plan.< >

关键词： Application specific integrated circuits Costs Power system planning Coupling circuits Power dissipation Data acquisition Production Testing Performance evaluation Control systems

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A knowledge based project plan generation and control system for ASIC design management

A knowledge based project plan generation and control system...

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Custom Integrated Circuits Conference (CICC)

作者： K.D. Muller-Glaser K. Neusinger K. Kirsch Institute of Computer Aided Circuit Design University Erlangen-Nuünberg Erlangen Germany

To enhance project planning and feasibility study for ASIC (application-specific integrated circuit) design, a project plan generation system has been developed which differs from known project management systems in the following features. It generates alternative ASIC design project plans and cost estimations by processing ASIC requirement specification data, estimation data for complexity, area, speed, and power dissipation and information from a design style specific knowledge base (digital, analog, gate array, standard cell, full custom), which includes data about design tools, hardware resources, development staff, and design specific economic data. Generation is supported by a set of design specific rules. A project control system allows the manager to control execution of the ASIC design project, to modify the generated project plan, to regenerate a different project plan, and to control activities of the development staff. When the project is finished, planned and actual data are compared and gained experience is stored back into the knowledge base.< >

关键词： Control systems Application specific integrated circuits Project management Power generation Costs Power dissipation Standards development Hardware Power system economics Power generation economics

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Using target faults to achieve a minimized partial scan path

Using target faults to achieve a minimized partial scan path

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VLSI Test Symposium

作者： H.H.S. Gundlach B. Koch K.-D. Muller-Glaser Institute for Computer Aided Circuit Design University Erlangen-Nuünberg Erlangen Germany

Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults, have to be addressed using partial scan. Different methods are given to adapt a partial scan path to the target faults. They do not depend on ATPG and therefore have very short runtimes. Results on sequential ATPG-benchmarks show that a strong reduction in the size of the partial scan path is possible. Also the combination of the structural selection and the selection with respect to target faults is proposed. First results prove its effectiveness.< >

关键词： Circuit testing Circuit faults Automatic test pattern generation Electrical fault detection Fault detection Feedback loop design for testability Integrated circuit measurements Algorithm design and analysis Circuit synthesis

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