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IMPROVED DETERMINISTIC TEST PATTERN GENERATION WITH APPLICATIONS TO REDUNDANCY IDENTIFICATION

IEEE TRANSACTIONS ON computer-aided design OF INTEGRATED CIRCUITS AND SYSTEMS 1989年第7期8卷 811-816页

作者： SCHULZ, MH AUTH, E Institute of Computer-Aided Design Department of Electrical Engineering Technical University Munich Munich Germany

The authors present several concepts and techniques aiming at a further improvement and acceleration of the deterministic test-pattern-generation and redundancy identification process. In particular, they describe an improved implication procedure and an improved unique sensitization procedure. While the improved implication procedure takes advantage of the dynamic application of a learning procedure, the improved unique sensitization procedure profits from a dynamic and careful consideration of the existing situation of value assignments in the circuit. As a result of the application of the proposed techniques, SOCRATES is capable of both successfully generating a test pattern for all testable faults in a set of combinational benchmark circuits, and of identifying all redundant faults with less than ten backtrackings.< >

关键词： Test pattern generators Circuit testing Circuit faults Redundancy Electron devices Fault diagnosis CMOS technology Switches Automatic testing

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COMPARATIVE STRUCTURAL LIFE ASSESSMENT OF PATROL BOAT BOTTOM PLATING

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NAVAL ENGINEERS JOURNAL 1990年第3期102卷 253-262页

作者： AYYUB, BM WHITE, GJ BELLWRIGHT, TF PURCELL, ES Bilal M. Ayyub:is currently an associate professor of civil engineering at the University of Maryland. He received his B.S. degree in civil engineering from the University of Kuwait in 1980. He completed both his M.S. (1981) and Ph.D. (1983) in civil engineering at the Georgia Institute of Technology. Dr. Ayyub has an extensive background in risk-based analysis. He is engaged in research work involving structural reliability marine structures and mathematical modeling using the theories of probability statistics and fuzzy sets. His research work has been sponsored by the National Transportation Safety Board National Science Foundation U.S. Coast Guard Department of Defense State of Maryland and University of Maryland. He is the author of more than 100 publications in national and international journals conference proceedings and reports. Dr. Ayyub was a recipient of the ASNE “Jimmie” Hamilton Award for 1985 the ASCE “Outstanding Research Oriented Paper” in theJournal of Water Resources Planning and Managementfor 1987 and Edmund Friedman Young Engineer Award for Professional Achievement from ASCE for 1989. Gregory J. White:is an associate professor of naval architecture at the U.S. Naval Academy. He received his B.S. degreein engineering mechanics from Vanderbilt University in 1975 an M.E. degree in naval architecture from the University of California Berkeley in 1981 and a Ph.D. in civil engineering (structures) from the University of Maryland in 1986. Dr. White served on active duty with the U.S. Navy from 1975 to 1979 as a junior officer in the engineering and operations departments of Pacific Fleet destroyers. Prior to coming to the Naval Academy he worked at Mare Island Naval Shipyard in the scientific code and in the R&D division of Exxon International company's Tanker Department. Dr. White is the author of more than two dozen technical articles and reports and is one of the U.S. representatives to the International Ship and Offshore Structures Congress (ISSC). His research interests lie in t

The estimation of an absolute life expectancy of a structure is a complex process and the results are expected to have relatively large levels of uncertainty. In this study, a comparative analysis is undertaken between two different patrol boats. This is an approach which results in a higher confidence level because certain factors common to both boats can be eliminated by assuming them to be at constant normal levels. The study is limited to the critical forward bottom plating and takes into account the differences in material, plate dimensions, operational profile, structure and loading of the two vessels. Two failure modes, plastic plate deformation and fatigue, are considered, and a novel approach to plate wastage is included. Many factors affect the structural life of a vessel. They include structural type, operational profile, structural details, loads, inspection and maintenance, design methods, safety factors, corrosion, and environmental factors. There are three types of uncertainty associated with these factors; namely, physical randomness, statistical uncertainties, and model uncertainties. The method described is designed to address these uncertainties. The objective of the paper is to present the reliability-based structural life assessment method, and then to use it to evaluate and compare the structural performance of the forward bottom plating of the two patrol boats. The results of the evaluation are presented in the form of graphs and tables in order to facilitate the comparative evaluation. The method is performed within a computer-based format which allows parametric sensitivity analysis of several variables including the size of the plating panel, thickness, operational profile and loading. The sensitivity of the structural life expectancy of the forward bottom plating to variations in these parameters is evaluated.

关键词： Naval Vessels

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ESSENTIAL: an efficient self-learning test pattern generation algorithm for sequential circuits

ESSENTIAL: an efficient self-learning test pattern generatio...

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IEEE International Test Conference

作者： M.H. Schulz E. Auth Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany

The authors present ESSENTIAL, deterministic automatic test pattern generation algorithm for sequential circuits. By combining reverse time processing over time frames and forward processing within time frames, ESSENTIAL avoids the detrimental a priori determination of a topological path to be sensitized or of a primary output, to which the fault effects have to be propagated. Moreover, the proposed test generation approach fully exploits the beneficial techniques that have successfully been used for combinational circuits by the automatic test pattern generation system SOCRATES. In particular, the authors discuss a learning procedure for global implications not only over reconvergent fanout, but also over time frames as well as static and dynamic unique sensitization techniques. After introducing a couple of intelligent heuristics employed for guiding and supporting the decision-making process, the authors report some preliminary but encouraging experimental results.< >

关键词： Test pattern generators Automatic test pattern generation Circuit testing Sequential circuits Circuit faults Automatic testing System testing Combinational circuits Coupling circuits Decision making

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Parallel Pattern Fault Simulation of Path Delay Faults

Parallel Pattern Fault Simulation of Path Delay Faults

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design Automation Conference

作者： M.H. Schulz F. Fink K. Fuchs Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany

This paper presents an accelerated fault simulation approach for path delay faults. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and non-robust detection of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.

关键词： Delay Circuit faults Circuit testing Fault detection Timing Computational modeling Circuit simulation Permission Logic testing Parallel processing

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Advanced automatic test pattern generation techniques for path delay faults

Advanced automatic test pattern generation techniques for pa...

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International Symposium on Fault-Tolerant Computing (FTCS)

作者： M.H. Schulz K. Fuchs F. Fink Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany

Based on the sophisticated techniques applied in the automatic test pattern generation system SOCRATES, the authors present the extension of SOCRATES to test generation for path delay faults. In particular, they propose a ten-valued logic and describe the corresponding implication and path sensitization procedures in detail. After discussing an extended multiple backtrace procedure, which has been developed specifically to meet the requirements of path delay testing, they conclude with a number of experimental results.< >

关键词： Automatic test pattern generation Delay Circuit faults Circuit testing System testing Test pattern generators Timing Latches Logic testing Clocks

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A three-valued fast fault simulator for scan-based VLSI-logic

A three-valued fast fault simulator for scan-based VLSI-logi...

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European Test Conference

作者： M.H. Schulz D. Pellkofer Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany

Based on an effective three-valued coding, the methods of two-valued fault simulation are extended to three-valued fault simulation. Solidly and potentially detected faults are considered. Parallel processing of patterns is applied at all stages of the calculation procedure, and the expensive fault simulation is restricted to fanout stems by adopting the concept of fanout-free regions. In addition, the exploitation of the dominance relationships between signals of a combinational circuit is shown to lead not only to an acceleration of the fault-simulation process, but also to improvements in fault-detection accuracy. Experimental benchmark results substantiate the efficiency of the approach and demonstrate that three-valued fault simulation can be almost as fast as two-valued fault simulation.< >

关键词： Circuit faults Circuit simulation Electrical fault detection Circuit testing Fault detection Computational modeling Combinational circuits computer simulation Parallel processing Logic circuits

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Hierarchical fault simulation in combinational circuits

Hierarchical fault simulation in combinational circuits

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European Test Conference

作者： M.H. Schulz B.H. Seiss F. Brglez Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany Bell-Northern Research Inc. NC USA

A method is presented for speeding up fault simulation in combinational circuits by taking advantage of a hierarchical circuit description. The parallel-pattern single-fault-propagation technique is combined with the concept of fanout-free regions, and this approach is then extended to exploit hierarchy. A number of illustrative experiments demonstrate the efficiency of the proposed method and substantiate the gains in simulation speed. Besides the savings in CPU time, the method results in a significant reduction in the memory requirements for creating and maintaining the computational model of the circuit to be simulated.< >

关键词： Circuit faults Circuit simulation Combinational circuits Computational modeling Very large scale integration Circuit testing Costs Automatic test pattern generation Artificial intelligence Acceleration

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Hierarchical test pattern generation based on high-level primitives

Hierarchical test pattern generation based on high-level pri...

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IEEE International Test Conference

作者： T.M. Sarfert R. Markgraf E. Trischler M.H. Schulz Department E STE 44 Siemens AG Munich Germany Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany

It is demonstrated that the exploitation of high-level primitives (HLPs) and, in particular, of the knowledge concerning their function in ATPG (automatic test pattern generation) leads to significant improvements in implication, unique sensitization, and multiple backtrace. Motivated by this observation and the necessity of covering all faults inside HLPs, the authors present the extension of the ATPG system SOCRATES to hierarchical test pattern generation, which is based upon HLPs and the strategy of dynamically expanding the HLPs to their gate-level realization, at most one at a time. Experimental results have substantiated that the proposed approach performs significantly better in terms of CPU time, elapsed time, fault coverage, and memory requirements than a gate-level ATPG algorithm. It is expected that the extended SOCRATES algorithm will be capable of coping with circuits consisting of 100000 gates and more within reasonable times, even in a workstation environment.< >

关键词： Test pattern generators Circuit faults Multiplexing Circuit testing Combinational circuits design methodology Logic arrays Very large scale integration Complexity theory Transistors

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computer-aided STRENGTH CALCULATION SYSTEM

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computerS & graphics 1988年第3-4期12卷 415-424页

作者： VELIKHOV, EP BETELIN, VB VISHNJAKOV, JS STAVITSKIJ, AI Institute of Computer-Aided Design Moscow USSR

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ESTIMATION OF STRUCTURAL SERVICE LIFE OF SHIPS

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NAVAL ENGINEERS JOURNAL 1989年第3期101卷 156-166页

作者： AYYUB, BM WHITE, GJ PURCELL, ES P.E. Bilal M. Ayyub:is currently an associate professor of civil engineering at the University of Maryland. He received his B.S. degree in civil engineering from the University of Kuwait in 1980. He completed both his M.S. (1981) and Ph.D. (1983) in civil engineering at the Georgia Institute of Technology. Dr. Ayyub has an extensive background in risk-based analysis and design simulation and construction engineering. He is engaged in research work involving structural reliability bridges marine structures and mathematical modeling using the theories of probability statistics and fuzzy sets. His research work is sponsored by the National Transportation Safety Board the National Science Foundation the U.S. Coast Guard the State of Maryland and the University of Maryland. Dr. Ayyub is a member of ASNE the American Society of Civil Engineers (ASCE) the American Concrete Institute (ACI) the Committee on Forensic Engineering of ASCE and the Committee on Structural Safety of ACI. He is the author of more than three dozen publications in national and international journals conference proceedings and reports. Dr. Ayyub received the ASNE “Jimmie” Hamilton Award for 1985 and the ASCE “Outstanding Research Oriented Paper” in the Journal of Water Resources Planning and Management for 1987. Gregory J. White:is an associate professor of naval architecture at the U.S. Naval Academy. He received his B.S. degree in engineering mechanics from Vanderbilt University in 1975 an M.E. degree in naval architecture from the University of California Berkeley in 1981 and a Ph.D. in civil engineering (structures) from the University of Maryland in 1986. Dr. White served on active duty with the U.S. Navy from 1975 to 1979 as a junior officer in the engineering and operations departments of Pacific Fleet destroyers. Prior to coming to the Naval Academy he worked at Mare Island Naval Shipyard in the scientific code and in the R&D division of Exxon International Company's Tanker Department. Dr. White is a lieutenant commande

A methodology for the structural life assessment of a ship's structure is suggested. The methodology is based on probabilistic analysis using reliability concepts and the statistics of extremes. In this approach, the estimation of structural life expectancy is based on selected failure modes. All possible failure modes of the ship must be investigated and the most likely paths to structural failure identified. For the purpose of illustration two failure modes are considered in this study. They are plate plastic deformation and fatigue cracking. Structural life based on these two failure modes is determined for an example vessel. The methodology determines the probability of failure of the ship's structural components according to the identified failure modes as a function of time. The results can be interpreted as the cumulative probability distribution function (CDF) of structural life. Due to the unknown level of statistical correlation between failure modes, limits or bounds on the CDF of the structural life are established. The limits correspond to the extreme cases of fully correlated and independent failure modes. The CDFs of structural life are determined for two inspection strategies; namely, inspection every year and inspection every two years with a warranty inspection at the end of the first year. The meaning of the results for the case investigated in this study is that, for example, given an inspection strategy of two years and a desired life of 15 years, there is a 72% chance that the vessel will not experience enough partial damage‘ in the failure modes identified to constitute reaching the “end of structural life” as defined.

关键词： Ships

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